TNETV1647GSTZWT datasheet(91/236 Pages) TI1

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TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

5.2

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

1.00

1.05

1.10

Supply voltage, Core (CVDD, VDDA_1P1V, USB_VDDA1P2LDO

(1),

CVDD

CVDDDSP)

(2)

1.15

1.2

1.25

Supply voltage, I/O, 3.3V (DVDD33, USB_DVDDA3P3)

3.15

3.3

3.45

DVDD

Supply voltage, I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL, PLLVDD18,

1.71

1.8

1.89

VDDA_1P8V, USB_VDD1P8, MXVDD, M24VDD)

Supply ground (VSS, VSSA_1P8V, VSSA_1P1V, DDR_VSSDLL,

VSS

USB_VSSREF, USB_VSS1P8, USB_VSSA3P3, USB_VSSA1P2LDO,

MXVSS

(3), M24V

(3))

DDR_VREF

DDR2 reference voltage(4)

0.49DVDDR2

0.5DVDDR2

0.51DVDDR2

DDR_ZP

DDR2 impedance control, connected via 200

Ω resistor to VSS

VSS

DDR_ZN

DDR2 impedance control, connected via 200

Ω resistor to DVDDR2

DVDDR2

DAC_VREF

DAC reference voltage input

0.475

0.5

0.525

DAC_RBIAS

DAC biasing, connected via 4 k

Ω resistor to VSSA_1P8V

VSSA_1P8V

USB_VBUS

USB external charge pump input

4.75

5.25

High-level input voltage, I/O, 3.3V

VIH

High-level input voltage, non-DDR I/O, 1.8V

0.65DVDD

Low-level input voltage, I/O, 3.3V

0.8

VIL

Low-level input voltage, non-DDR I/O, 1.8V

0.35DVDD

Operating case temperature

Default

°C

1.05 V core

405

FSYSCLK1

DSP Operating Frequency (SYSCLK1)

MHz

1.2 V core

513

(1)

This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO.

(2)

Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2, 1.26 V with ±3% tolerances) by implementing simple board changes such as reference resistor values or input pin

configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC

devices.

(3)

Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground.

(4)

DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2.

Device Operating Conditions

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