TNETV1647GSTZWT datasheet(28/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

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2.7

Terminal Functions

The terminal functions tables (Table 2-5 through Table 2-30) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin

has any internal pullup or pulldown resistors, and a functional pin description. For more detailed

information on device configuration, peripheral selection, multiplexed/shared pin, and debugging

considerations, see Section 3, Device Configurations, of this data manual.

Table 2-5. BOOT Terminal Functions

SIGNAL

OTHER(2)

TYPE(1)

DESCRIPTION

(3)

NAME

NO.

BOOT

These pins are multiplexed between ARM boot mode and the VPBE. At

reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to

COUT0/

IPD

determine the ARM boot configuration. See below for the boot modes set

B3/

A16

I/O/Z

DVDD18

by these inputs. See Section 3.3, Bootmode, for more details.

BTSEL0

After reset, these are video encoder outputs COUT0 and COUT1, or

RGB666/888 Blue output data bits 3 and 4 B3/B4.

BTSEL1

BTSEL0

ARM Boot Mode

ARM ROM boot (NAND, SPI) [default]

COUT1/

IPD

B4/

B16

I/O/Z

ARM EMIFA boot (NOR)

DVDD18

BTSEL1

ARM ROM boot (HPI)

ARM ROM boot (UART0)

This pin is multiplexed between EMIFA and the VPBE. At reset, the input

state is sampled to set the EMIFA data bus width (EM_WIDTH). For an

COUT2/

IPD

8-bit-wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data

B5/

A17

I/O/Z

DVDD18

bus, EM_WIDTH = 1.

EM_WIDTH

After reset, it is video encoder output COUT2 or RGB666/888 Blue output

data bit 5 B5.

This pin is multiplexed between DSP boot and the VPBE. At reset, the

input state is sampled to set the DSP boot source DSP_BT. The DSP is

COUT3/

IPD

booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when

B6/

B17

I/O/Z

DVDD18

DSP_BT=1.

DSP_BT

After reset, it is video encoder output COUT3 or RGB666/888 Blue data

bit 6 output B6.

YOUT0/

IPD

G5/

D15

I/O/Z

DVDD18

AEAW0

YOUT1/

IPD

G6/

D16

I/O/Z

DVDD18

AEAW1

These pins are multiplexed between EMIFA and the VPBE. At reset, the

YOUT2/

input states of AEAW[4:0] are sampled to set the EMIFA address bus

IPD

G7/

D17

I/O/Z

width. See Section 3.4.2, Peripheral Selection at Device Reset, for details.

DVDD18

AEAW2

After reset, these are video encoder outputs YOUT[0:4] or RGB666/888

Red and Green data bit outputs G5, G6, G7, R3, and R4.

YOUT3/

IPD

R3/

D18

I/O/Z

DVDD18

AEAW3

YOUT4/

IPD

R4/

E15

I/O/Z

DVDD18

AEAW4

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-k

Ω resistor should be used.)

(3)

Specifies the operating I/O supply voltage for each signal

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