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TNETV1647GSTZWT Datasheet(PDF) 95 Page - Texas Instruments |
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TNETV1647GSTZWT Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 236 page ![]() CV DD CV DDDSP 1 CV DD DV DDXX (A) Note A:DV denotesallI/Osupplies. DDXX 1 TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4) 1.05 V and 1.2 V NO. UNIT MIN MAX 1 td(CVDD-CVDDDSP) Delay time, CVDD supply ready to CVDDDSP supply ramp start 0 (1) ns (1) In host-boot mode, the CVDDDSP supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON and DSP power domains. Figure 6-4. DSP Host-Boot Mode Core Supply Timings Once the CVDD supply has been powered up, the I/O supplies may be powered up. Table 6-2 and Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DVDDXX is used to denote all I/O supplies. NOTE The DVDDXX supply power-up is specified relative to the CVDD supply power-up, not the CVDDDSP supply. Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5) 1.05 V and 1.2 V NO. UNIT MIN MAX 1 td(CVDD-DVDD) Delay time, CVDD supply ready to DVDDXX supply ramp start 0 100 ms Figure 6-5. I/O Supply Timings There is not a specific power-up sequence that must be followed with respect to the order of the power-up of the DVDD18, DVDDR2, and DVDD33 supplies. Once the CVDD supply is powered up and the td(CVDD-DVDDXX) specification is met, the DVDD18, DVDDR2, and DVDD33 supplies may be powered up in any order of preference. All other supplies may also be powered up in any order of preference once the td(CVDD-DVDDXX) specification has been met. Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 95 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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