ST7DALIF2 datasheet(58/171 Pages) STMICROELECTRONICS

58 / 171 page

Power saving modes

ST7DALIF2

58/171

Figure 29.

AWUFH mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 15: Interrupt mapping on page 47 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see

Figure 11).

11.6.1

AWUFH control/status register (AWUCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:3 = Reserved.

RESET

INTERRUPT 3)

CPU

MAIN OSC

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY5)

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

AWU RC OSC

OFF

AWU RC OSC

OFF

HALT INSTRUCTION

(Active-halt disabled)

(AWUCSR.AWUEN=1)

000

AWU

AWUM

AWUEN

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