ST7DALIF2 datasheet(66/171 Pages) STMICROELECTRONICS

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I/O ports

ST7DALIF2

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12.3

I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR

registers and specific I/O port features such as ADC input or open drain.

Switching these I/O ports from one state to another should be done in a sequence that

prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31.

Other transitions are potentially risky and should be avoided, since they may present

unwanted side-effects such as spurious interrupt generation.

Figure 31.

Interrupt I/O port state transitions

12.4

Unused I/O pins

Unused I/O pins must be connected to fixed voltage levels. Refer to Section 20.

12.5

Low power modes

12.6

Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is

selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM

instruction).

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

Table 27.

Effect of low power modes on I/O ports

Mode

Description

Wait

No effect on I/O ports. External interrupts cause the device to exit from Wait

mode.

Halt

No effect on I/O ports. External interrupts cause the device to exit from Halt

mode.

Table 28.

I/O port interrupt control/wake-up capability

Interrupt event

Event

flag

Enable

control

bit

Exit

from

Wait

Exit

from

Halt

External interrupt on selected

external event

DDRx

ORx

Yes

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