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ST7DALIF2

Watchdog timer (WDG)

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Watchdog timer (WDG)

13.1

Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated

by external interference or by unforeseen logical conditions, which causes the application

program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on

expiry of a programmed time period, unless the program refreshes the counter’s contents

before the T6 bit becomes cleared.

13.2

Main features

■ Programmable free-running downcounter (64 increments of 16000 CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit reaches zero

■ Optional reset on HALT instruction (configurable by option byte)

■ Hardware Watchdog selectable by option byte

13.3

Functional description

The counter value stored in the CR register (bits T[6:0]), is decremented every 16000

machine cycles, and the length of the timeout period can be programmed by the user in 64

increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls

over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin

for typically 30 µs.

Figure 32.

Watchdog block diagram

The application program must write in the CR register at regular intervals during normal

operation to prevent an MCU reset. This downcounter is free-running: it counts down even if

RESET

WDGA

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷16000

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