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Data Sheet

AD9545

Rev. A | Page 63 of 157

DISTRIBUTION EMBEDDED OUTPUT CLOCK MODULATION

MODULATION CONTROLLER OVERVIEW

The AD9545 has the capability to embed a low frequency clock

within a high frequency carrier. Referring to Figure 48, only the

primary output of a Q divider pair routes to the modulation

controller, whereas the secondary output bypasses the modulation

controller and routes directly to the N-shot/PRBS controller. Thus,

only the primary distribution clock outputs support embedded

clock modulation capability (for example, Output OUT0AP

supports modulation whereas Output OUT0AN does not).

Embedded clock modulation consists of dynamically varying

the pulse width of the designated Q divider output clock, where

each variation of the pulse width constitutes a modulation

event. A modulation event always spans two Q divider clock

cycles (see the Balanced and Unbalanced Modulation section).

An expanded diagram of the modulation controller appears in

Figure 54. Although Figure 54 is specific to PLL Channel 0, it is

also representative of PLL Channel 1, because there is a

dedicated modulation controller for each PLL channel.

Any one or more single-letter Q divider outputs (for example,

Q0A but not Q0AA) can operate as an embedded clock modulator.

To enable embedded modulation, program the appropriate enable

Qxy modulator bits (where x is 0 or 1 and y is A, B or C) in Bit D0

of Register 0x10CF to Register 0x10D1 and Register 0x14CF to

embedded clock modulation, whereas Logic 0 (default)

bypasses the modulation controller (via the mux in Figure 54).

MODULATION CONTROLLER

MODULATOR A

ENABLE Q0A

N-SHOT MODULATOR

MODULATOR B

ENABLE Q0A MODULATOR

MODULATION STEP

Q0A MODULATION COUNTER

MODULATOR C

OUT

MODULATION

BLOCK

TRIGGER

MODE

STEP

TRIGGER

MODE

STEP

SIGA

SNCA

INA

INB

INC

SYNC

SIGB

SNCB

SIGC

SNCC

SIGAA

SIGBB

SIGCC

Q0A

Q0AA

Q0B

Q0BB

Q0C

Q0CC

TRIGGER

MODE

TEXT

= BIT(S) IN THE REGISTER MAP

Q0A MODULATOR POLARITY

ENABLE Q0A SINGLE-PULSE MODULATOR

Figure 54. Block Diagram of Embedded Clock Modulation Controller

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