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Data Sheet

AD9545

Rev. A | Page 85 of 157

value from 0 through 7, corresponding to a particular source

profile).

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. When the water level

is below the low water mark (−1025), the lock detector indicates

an unlock condition. Conversely, when the water level is above

the high water mark (+1024), the lock detector indicates a lock

condition. When the water level is between the marks, the lock

detector holds its last condition. Figure 73 shows this concept

with an overlay of an example of the instantaneous water level

(vertical) vs. time (horizontal) and the resulting lock/unlock

states.

2047

–2048

1024

–1025

LOCK LEVEL

UNLOCK LEVEL

LOCKED

UNLOCKED

STATE

RATE

DRAIN

RATE

Figure 73. Lock Detector Diagram

During any given PFD phase error sample, the lock detector

either adds water with the fill bucket or removes water with the

drain bucket (one or the other, but not both). The decision of

whether to add or remove water depends on the threshold level

specified by the user in the 24-bit unsigned Profile x phase lock

threshold bit field. The bit field value is the desired threshold in

picoseconds. Thus, the phase lock threshold extends from 0 ps

to 16.7 µs and represents the phase error at the output of the

PFD. Though the programming range supports 0 ps as a lower

limit, in practice, the minimum value must be greater than 50 ps.

The phase lock detector compares the absolute value of each

phase error sample at the output of the PFD to the programmed

phase threshold value. If the absolute value of the phase error

sample is less than or equal to the programmed phase threshold

value, the detector control logic adds one fill bucket into the

tub. Otherwise, it removes one drain bucket from the tub. Note

that it is the magnitude, relative to the phase threshold value,

that determines whether to fill or drain the bucket, and not the

polarity of the phase error sample.

An exception to the fill/drain process occurs when the phase

slew limiter is active. When the phase slew limiter is actively in

the limiting process, the lock detector blocks fill events, allowing

only drain events to occur.

When more filling is taking place than draining, the water level

in the tub eventually rises above the high water mark (+1024),

which causes the lock detector to indicate lock. When more

draining is taking place than filling, the water level in the tub

eventually falls below the low water mark (−1024), which causes

the lock detector to indicate unlock. The ability to specify the

threshold level, fill rate, and drain rate enables the user to tailor

the operation of the lock detector to the statistics of the timing

jitter associated with the input reference signal. Note that, for

debug purposes, the user can make the fill or drain rate zero to

force the lock detector to indicate a lock or unlock state,

respectively.

Whenever the AD9545 enters freerun or holdover mode, the

DPLL phase lock detector indicates an unlocked state.

For more information on how to choose the appropriate phase

lock threshold, fill rate, and drain rate values for a given

application, refer to the AN-1061 Application Note.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that

of the phase lock detector, with two exceptions:

•

The fill or drain decision is based on the period deviation

between the reference of the DPLL and the feedback

signals, instead of the phase error at the output of the PFD.

•

The frequency lock detector is unaffected by the state of

the phase slew limiter.

The frequency lock detector provides the user with a dynamic

status bit, DPLLx frequency lock (where x is 0 or 1), located in

Bit D2 of Register 0x3100 and Register 0x3200. However,

because this bit is dynamic in nature, the recommendation is to

use the IRQ mechanism for frequency lock indication (see

below).

The DPLLx frequency locked and DPLLx frequency unlocked

bit pairs (where x is 0 or 1) indicate when the DPLL frequency

lock detector changes states via Register 0x3010, Bits[3:2] and

latches to Logic 1 when the DPLL changes state from not

frequency locked to frequency locked. The DPLLx frequency

unlocked bit latches to Logic 1 when the DPLL changes state

from frequency locked to not frequency locked. Because these

are latched bits, they may represent a condition that is no longer

true. Therefore, the user must clear these bits (via the Register

0x200B, Bits[3:2] and Register 0x2010, Bits[3:2]) to obtain

visibility of subsequent state transitions of the frequency lock

detector (see the Interrupt Request (IRQ) section).

The frequency lock detector uses the 24-bit unsigned Profile x

frequency lock threshold bit field specified in units of picoseconds

(where x is a value from 0 through 7 corresponding to a particular

source profile) in registers starting with Address 0x0805,

Address 0x0825, Address 0x0845, Address 0x0865, Address

0x0885, Address 0x08A5, Address 0x08C5, and Address 0x08E5.

Thus, the frequency threshold value extends from 0 ps to

16.7 µs. It represents the absolute value of the difference in

period between the reference and feedback signals at the input

to the DPLL.

Profile x frequency lock threshold = |1/fREF − 1/fFB|/10−12

where:

fREF is the frequency of the signal at the DPLL PFD reference input.

fFB is the frequency of the signal at the DPLL PFD feedback input.

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