AD9545 datasheet(89/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 89 of 157

Because the DPLL feedback loop results in an average offset of

zero between the two inputs of the digital phase detector, tOFST

translates to the DPLL output with the polarity shown in Figure 74.

The signed nature of the DPLLx phase offset bit field means the

user can advance or delay the DPLL output signal relative to its

input. A positive value for tOFST delays the output signal relative to

the input signal. That is, the output edge occurs later. Conversely, a

negative value advances the output signal relative to the input

signal; therefore, the output edge occurs earlier.

The relationship between tOFST (seconds) and the value of the

DPLLx phase offset bit field is

DPLLx Phase Offset = tOFST

/10−12

For example, find the value of the DPLLx phase offset bit field

necessary to advance the output signal by 75 ns (that is, tOFST =

−75 ns).

DPLLx Phase Offset = (−75 × 10−9

)/10−12

= −75,000

= 0xFFFFFEDB08 (hexadecimal)

TUNING WORD OFFSET CLAMP

The DPLL contains a frequency clamp that places bounds on

the frequency range of the DPLL output. The frequency clamp

feature is beneficial for applications in which downstream

devices cannot tolerate frequencies beyond prescribed limits.

The clamp feature, as shown in Figure 75, uses the 24-bit

unsigned DPLLx freerun tuning word offset clamp bit field

(where x is 0 or 1) in Register 0x1006 to Register 0x1008 and

feature is always active. However, the default value of the DPLLx

freerun tuning word offset clamp bit field is a maximum value,

which establishes a default frequency clamp limit of approximately

±586 kHz (for a system clock frequency of 2.4 GHz). An NCO

output frequency of 320 MHz equates to an offset of

approximately 1800 ppm (or 0.018%).

DIGITAL

PHASE

DETECTOR

N-DIVIDER

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

DPLLx FREERUN

TUNING WORD

LOOP

CONTROLLER

XOA XOB

AD9545

TDC

DPLLx FREERUN TUNING

WORD OFFSET CLAMP

TEXT

= BIT(S) IN THE REGISTER MAP

Figure 75. Tuning Word Offset Clamp Feature

The frequency offset, fCLAMP, defines the separation between a

center frequency, f0, and the upper and lower frequency bounds

as shown in Figure 76. The Example A traces show f0 as a fixed

value over time, whereas the Example B traces show the center

frequency can assume different values over time.

FREQUENCY

TIME

fCLAMP

EXAMPLE A

EXAMPLE B

Figure 76. Example Frequency Clamp Plot

The center frequency (f0) for the frequency clamp feature has

three possible sources. One source is the DPLLx freerun tuning

word bit field (where x is 0 or 1). This source is in effect when

DPLLx force freerun = 1 (where x is 0 or 1) in Bit D0 of Register

0x2105 and Register 0x2205.

The second source of f0 is the DPLL loop filter. This source is in

effect when the tuning word history feature is either inactive or is

active but has not had sufficient time to produce a valid result.

The final source of f0 is the output of the tuning word history block

(see the Tuning Word History section). This source is in effect

when the tuning word history feature is active and the tuning

word history block has had sufficient time to produce a valid result.

Switching between DPLL operating modes (freerun to active to

holdover, for example) results in different sources of f0; therefore,

the frequency clamp function tends to behave like Example B in

Figure 76.

The relationship between fCLAMP, the system clock frequency (fS),

and the value of the DPLLx freerun tuning word offset clamp

bit field is as follows:

fCLAMP

= DPLLx Freerun Tuning word Offset Clamp × (fS/236)

For example, assume a system clock frequency of 2.4 GHz and a

desired frequency offset clamp limit of ±10 kHz (that is fCLAMP =

104). Solving the fCLAMP equation for the DPLLx freerun tuning

word offset clamp bit field, DPLLx FTWOC, yields

DPLLx FTWOC = 236 × fCLAMP/fS

(20)

= 236 × 104/(2.4 × 109)

= 286,331 (nearest integer)

= 0x045E7B (hexadecimal)

In some cases, it is more useful to specify fCLAMP as a fractional

offset of the NCO output frequency (in percent or parts per

million, for example).

Assume a system clock frequency of 2.4 GHz, an NCO output

frequency of 250 MHz and a desired frequency offset clamp

limit of 25 ppm (25 × 10−6). Solve for fCLAMP as

fCLAMP = 25 × 10−6 × 250 MHz

= 6250 Hz

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