AD9545 datasheet(100/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 100 of 157

ANALOG PLL (APLL)

APLL OVERVIEW

Figure 81 shows a block diagram of the APLL, which is valid for

both APLL0 and APLL1. The main components of the APLL

comprise the following:

•

An integrated VCO

•

A combined phase/frequency detector (PFD) and charge

pump

•

A loop filter

•

A feedback divider (M-divider)

The purpose of the APLL is

•

To provide a low noise output clock signal

•

To upconvert the DPLL output frequency to ~3 GHz

•

To suppress the spurious artifacts of the NCO

VOLTAGE CONTROLLED OSCILLATOR (VCO)

The VCO provides a clean, low noise RF clock signal in the

3 GHz range that feeds the output distribution section, with

APLL0 as the source for the OUT0x outputs and APLL1 as the

source for the OUT1x outputs. The VCOs for APLL0 and

APLL1 cover nonoverlapping frequency ranges, as shown in

Table 46. The output frequency of the APPL is ½ its VCO

frequency due to the P-divider (see Figure 81).

Table 46. APLL VCO Frequency and Gain

APLL

VCO Frequency (MHz)

VCO Gain (MHz/V)

2424 to 3232

3232 to 4040

100

The VCO covers its approximately 800 MHz frequency range by

employing many narrow overlapping frequency bands. To

ensure the VCO uses the appropriate band for a given output

frequency and to accommodate proper operation over a broad

temperature range, the AD9545 incorporates an automated

VCO calibration feature.

VCO Calibration

To initiate VCO calibration of APLL0 or APLL1 independently,

write a Logic 1 to the appropriate calibrate APLLx bit (where x

is 0 or 1) in Bit D1 of Register 0x2100 and Register 0x2200. The

calibrate APLLx bit is not autoclearing; therefore, the user must

immediately restore these bits to Logic 0, because maintaining a

static Logic 1 state may cause unexpected device behavior.

To calibrate both APLL channels, the user can write a Logic 1 to

the calibrate all bit in Bit D1 of Register 0x2000 rather than

programming both calibrate APLLx bits. The calibrate all bit

calibrates the system clock PLL as well.

There are two options for checking the status of the APLL VCO

calibration process. One option is via Bits[5:4] of Register 0x3100

and Register 0x3200, which contain the APLLx calibration busy

and APLLx calibration done bits (where x is 0 or 1). Logic 1

constitutes the status indicated by the name of the bit. The other

option is via Bits[D1:D0] of Register 0x3014 and Register 0x3019,

which contain the APLLx calibration started and APLLx

calibration completed bits (where x is 0 or 1). Because these bits are

part of the IRQ mechanism (see the Interrupt Request (IRQ)

section), they constitute latched versions of the APLL calibration

busy and APLL calibration done bits. The user must clear the

APLLx calibration started and APLLx calibration completed

bits via Bits[D1:D0] of Register 0x200F and Register 0x2014 to

obtain visibility of subsequent state changes of the VCO

calibration process.

The APLL calibration busy status bit is also available as an

output signal via an appropriately configured Mx pin.

PHASE

DETECTOR AND

CHARGE PUMP

M-DIVIDER

VCO

CAL

LOCK

DETECTOR

APLLx MANUAL CHARGE PUMP CURRENT

LFx

LDOx

AD9545

TEXT

= BIT(S) IN THE REGISTER MAP

VCO

LOOP FILTER

FROM

DPLL

TO OUTPUT

DISTRIBUTION

CHARGE

PUMP

CONTROL

LOOP

FILTER

CONTROL

APLLx LOCK

APLLx UNLOCKED

ENABLE APLLx DC OFFSET CURRENT

APLLx DC OFFSET CURRENT DIRECTION

APLLx DC OFFSET CURRENT VALUE

APLLx LOOP FILTER ZERO RESISTOR (R1)

APLLx LOOP FILTER SECOND

POLE RESISTOR (R3)

APLLx LOOP FILTER POLE

CAPACITOR (C2)

CALIBRATE APLLx

APLLx CALIBRATION BUSY

APLLx CALIBRATION DONE

APLLx Mx

FEEDBACK DIVIDER

3.9nF

220nF

APLLx CALIBRATION START

APLLx CALIBRATION COMPLETE

ENABLE APLLx MANUAL CHARGE PUMP CURRENT

APLLx LOCKED

÷2

P-DIVIDER

Figure 81. APLL Block Diagram

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