AD9545 datasheet(80/157 Pages) AD

80 / 157 page

AD9545

Data Sheet

Rev. A | Page 80 of 157

DPLL FEEDBACK DIVIDER (N-DIVIDER)

The DPLL feedback N-divider consists of an integer and

fractional part. The fractional part, however, is only available in

buildout mode (see the Frequency Translation Loops section).

There are four unsigned 32-bit bit fields associated with the N-

divider as follows:

•

Profile x.y buildout N-divider

•

Profile x.y hitless N-divider

•

Profile x.y buildout fraction

•

Profile x.y buildout modulus

Although these four bit fields comprise 32 bits each, only the

lower 30 bits are useable as a valid divide ratio (that is, the two

most significant bits must always be zero). There are 12

occurrences of these bit fields: six occurrences associated with

the translation profiles for PLL0 and six associated with the

translation profiles for PLL1. These bit fields reside in the

The programming requirements for the N-divider depends on

the selected operating mode (see the Frequency Translation

Loops section).

N-Divider for Phase Buildout Mode

In phase buildout mode, the N-divider is an integer plus

fractional divider (N + FRAC/MOD). Note that changing the

value of N or MOD when the corresponding translation profile

is active causes the associated DPLL to reacquire its reference

input signal. However, the DPLL can accommodate on the fly

changes to the FRAC value without causing a reacquisition.

To program the value of N, use Profile x.y buildout N-divider

bit field (where x is 0 or 1 and y is a value from 0 to 5). The

Profile x.y buildout N-divider bit fields reside in registers

starting with Address 0x120C, Address 0x122C, Address 0x124C,

Address 0x126C, Address 0x128C, Address 0x12AC, Address

0x160C, Address 0x162C, Address 0x164C, Address 0x166C,

0x168C, and Address 0x16AC.

Program the Profile x.y buildout N-divider bit field with a value

one less than the desired divide ratio. As a result, the N-divider

provides integer divide ratios from 1 to 1,073,741,824.

For example, for a divide ratio of N = 1,000,000, the Profile x.y

buildout N-divider bit field value is 999,999 (0x000F423F

hexadecimal).

Programming the fractional part of the N-divider requires two

integers. One integer constitutes the numerator of the fraction

(FRAC). The other integer constitutes the denominator of the

fraction (MOD).

Program FRAC via the 24-bit unsigned Profile x.y buildout

fraction bit field (where x is 0 or 1 and y is a value from 0 to 5).

The Profile x.y buildout fraction bit fields reside in registers

starting with Address 0x1210, Address 0x1230, Address 0x1250,

Address 0x1270, Address 0x1290, Address 0x12B0, Address

0x1610, Address 0x1630, Address 0x1650, Address 0x1670,

Address 0x1690, and Address 0x16B0.

Program MOD via the 24-bit unsigned Profile x.y buildout

modulus bit field (where x is 0 or 1 and y is a value from 0 to 5).

MOD must satisfy the constraint: FRAC < MOD. The Profile x.y

buildout modulus bit fields reside in registers starting with

Address 0x1213, Address 0x1233, Address 0x1253, Address

0x1273, Address 0x1293, Address 0x12B3, Address 0x1613,

Address 0x1633, Address 0x1653, Address 0x1673, Address

0x1693, and Address 0x16B3.

For phase buildout applications requiring the N-divider to be

integer only, program MOD = 0, which disables the fractional

divide portion of the N-divider.

For example, suppose the desired fractional part of the N-divider is

0.387429. Then the corresponding fraction is FRAC/MOD =

387,429/1,000,000. Generally, one reduces the FRAC/MOD

fraction to its lowest terms, but in this example, the fraction is

irreducible. Therefore, the Profile x.y buildout fraction bit field

value is 387,429 (0x0005E965 hexadecimal) and the Profile x.y

buildout modulus bit field value is 1,000,000 (0x000F4240

hexadecimal).

N-Divider for Zero Delay Mode

In the zero delay modes, the AD9545 automatically disables the

fractional divide portion of the N-divider. That is, zero delay

(hitless) operation necessitates that the DPLL operate as an

integer-N PLL.

N-Divider in Internal Zero Delay Mode

Program N via the 32-bit unsigned Profile x.y hitless N-divider

bit field (where x is 0 or 1 and y is a value from 0 to 5). The

Profile x.y hitless N-divider bit fields reside in registers starting

with Address 0x1208, Address 0x1228, Address 0x1248,

Address 0x1268, Address 0x1288, Address 0x12A8, Address

0x1608, Address 0x1628, Address 0x1648, Address 0x1668,

Address 0x1688, and Address 0x16A8. The format of this bit

field is identical to the Profile x.y buildout N-divider bit field.

However, even though the device is operating in zero delay

(hitless) mode, the user must still program the Profile x.y

buildout N-divider bit field to ensure proper operation of the

DPLL loop filter. The divide ratio is the DPLL NCO frequency

divided by the frequency of the TDC associated with the DPLL

reference input and rounded to the nearest integer. In the case

of internal zero delay operation, the Profile x.y buildout N-

divider bit field value relates to the Profile x.y hitless N-divider

bit field value as follows (rounded to nearest integer):

NBUILDOUT

= NHITLESS × 2 × Q/M

whereQ is the Q divider and M is the M divider (see Figure 62).

N-Divider in External Zero Delay Mode

There is no internal feedback divider associated with the DPLL

in external zero delay operation, because the feedback path is

external. Therefore, there is no requirement to program the

Profile x.y hitless N-divider bit field. However, the user must

AD9545 Datasheet(PDF) 80 Page - Analog Devices

AD9545 Datasheet(HTML) 80 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL