AD9545 datasheet(84/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 84 of 157

The NCO applies adjustments to INT and FRAC as necessary

when the system clock compensation feature is active (see the

System Clock Compensation section.

NCO GAIN TUNING WORD FILTER BANDWIDTH

Although not explicitly shown in Figure 71, the NCO contains a

digital low pass filter, the NCO gain tuning word filter. This

filter has a single-pole response similar to a simple resistor and

capacitor low-pass filter (see Figure 72), but with a variable gain

component that compensates for the nonlinear gain of the

NCO. The NCO gain tuning word filter reduces frequency

transients that can occur when the DPLL switches between

closed-loop and open-loop operating modes (active to

holdover, for example).

To control the filter bandwidth use the 4-bit unsigned DPLLx

NCO gain filter bandwidth bit field (where x is 0 or 1) in

Bits[D3:D0] of Register 0x1009 and Register 0x1409 per

Table 42.

Table 42. NCO Gain Tuning Word Filter Bandwidth Selections

DPLLx NCO Gain

Filter Bandwidth Bit

Field Value

3 dB Bandwidth (Hz)

Transition

Time (ms)

248,000

0.003

124,000

0.006

62,000

0.013

31,000

0.026

15,500

0.051

7800

0.102

3900

0.204

1900

0.419

970

0.820

490

1.62

240

3.32

120

6.63

13.0

26.5

53.1

7.6

105

To prevent degradation of the phase margin associated with the

DPLL loop filter (see the DPLL Loop Filter section), the user

must be careful to choose an NCO gain tuning word filter

bandwidth from Table 42 that is at least 100 times greater than

the loop bandwidth of the DPLL. This value includes any

expansion of the DPLL loop filter bandwidth by the fast

acquisition block, if enabled (see the DPLL Fast Acquisition

(FACQ) Options section).

The NCO gain tuning word filter has implications when using

the NCO as a traditional, open-loop digital frequency synthesizer.

For example, when programming the AD9545 to freerun mode

(see the Freerun Tuning Word section), the DPLL operates like

a traditional NCO. That is, the user can program different

frequency tuning words to synthesize different frequencies. In a

traditional NCO, programming a new tuning word results in an

instantaneous switch from the initial frequency to the new

frequency (like the input trace shown in Figure 72). However, in

the case of the DPLL, when programming different tuning

words, the NCO transitions from one frequency to the next

smoothly based on the programmed bandwidth of the NCO

gain tuning word filter as shown in Figure 72 (see Table 42 for

the transition time to 99% of a step input).

TUNING

WORD

TIME

FTW2

FTW1

INPUT

OUTPUT

TRANSITION

TIME

Figure 72. NCO Gain Tuning Word Filter Response

DPLL LOCK DETECTORS

DPLL Phase Lock Detector

Each DPLL channel (DPLL0 and DPLL1) contains an all digital

phase lock detector. The user controls the threshold sensitivity

and hysteresis of the phase detector via the source profiles (see

the Source Profiles section).

The phase lock detector provides the user with a dynamic status

bit, DPLLx phase lock (where x is 0 or 1), located in Bit D1 of

is dynamic in nature, the recommendation is to use the IRQ

mechanism for phase lock indication.

The DPLLx phase locked and DPLLx phase unlocked bit pairs

(where x is 0 or 1) indicate when the DPLL phase lock detector

changes state via Bits[D1:D0] of Register 0x3010 and Register

0x3015. The DPLLx phase locked bit latches to Logic 1 when

the DPLL changes state from not phase locked to phase locked.

The DPLLx phase unlocked bit latches to Logic 1 when the

DPLL changes state from phase locked to not phase locked.

Because these are latched bits, they may represent a condition

that is no longer true. Therefore, the user must clear these bits

(via Bits[D1:D0] of Register 0x200B and Register 0x2010) to

obtain visibility of subsequent state transitions of the phase lock

detector (see the Interrupt Request (IRQ) section).

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 73). The total capacity of the tub

is 4096 units, with −2048 denoting empty, 0 denoting the 50%

point, and +2047 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark

at −1025 and a high water mark at +1024. To change the water

level, the phase lock detector adds water with a fill bucket or

removes water with a drain bucket. To specify the size of the fill

and drain buckets, use the unsigned 8-bit Profile x phase lock fill

rate and Profile x phase lock drain rate bit field (where x is a

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