AD9545 datasheet(68/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 68 of 157

DISTRIBUTION OUTPUT CLOCK SYNCHRONIZATION

SYNCHRONIZATION OVERVIEW

The AD9545 has a builtin synchronization controller that

provides the user with a flexible and sophisticated means to

synchronize its multiple output clock signals. The synchronization

controller properly sequences internal events to ensure proper

synchronizing of the output clocks of the device.

A particularly important aspect of the synchronization controller

involves the control of the output clocks following a device

power-up or reset. On power-up or reset, the synchronization

controller waits for a sync trigger before activating the output

clocks. Until a sync trigger occurs, the synchronization controller

holds all the distribution Q dividers in a reset state, which

prevents any clock signals from appearing at the OUTX pins.

Therefore, the user must initiate the synchronization sequence

to have any clock signals appear at the output.

There are three ways to trigger the synchronization sequence:

•

Manual sync via an Mx pin, via the sync all bit in Bit D3 of

(where x is 0 or 1) in Bit D3 of Register 0x2101 and

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•

Autoreconfiguration (changes to Q divider values)

•

Autosync

Autosync is the preferred option for output clock synchronization.

A sync trigger event is channel specific. That is, it applies to

either PLL Channel 0 or PLL Channel 1. The exception is a

manual sync, which can apply to both channels via the sync all

bit. Assertion of the sync all bit does not imply synchronization

of both channels relative to each other but causes a simultaneous

triggering of the synchronization process for both channels.

A sync trigger initiates the synchronization sequence. Following

a trigger event, the synchronization controller checks whether

the enable DPLLx reference sync bit of either PLL channel is set

set (Bit D2 of Register 0x10DB and Register 0x14DB). If so, the

synchronization controller waits for a hitless profile to become

valid before muting all outputs (because reference synchronization

is only viable for zero delay/hitless translation modes).

Next, the synchronization controller confirms that the output

drivers are muted, then puts the P-dividers and Q dividers in a

reset state (for the controller to load new Q divider

configuration information—for example, a new divide ratio).

Then the synchronization controller again checks whether the

enable DPLLx reference sync bit of either PLL channel is set so

that it can align the release of the output clocks with a rising

edge of the active reference. However, if the enable DPLLx

reference sync bit is clear, the synchronization controller checks

for release of manual sync (that is, a clearing of the sync all bit,

or a clearing of the sync all Channel x dividers bit (where x is 0

or 1). The synchronization controller also checks that the APLL

indicates calibrated and locked status before proceeding.

Next, the synchronization controller unmutes the output drivers

and releases the appropriate Q dividers from their reset state.

Finally, the synchronization controller returns to waiting for a

subsequent sync trigger.

The output clock synchronization sequence initiates only when

the system clock is locked and stable.

MANUAL SYNC TRIGGER

A manual sync trigger occurs when the user sets one of three

manual sync bits. The sync all bit initiates the synchronization

sequence for all of the AD9545 output clocks. Alternatively, the

user can synchronize only those outputs associated with one of

the PLL channels via the sync all Channel x dividers bit. The

same synchronization features available via these bits are also

available via any of the Mx pins configured as an input.

Setting any of the manual sync bits causes the synchronization

sequence to execute up to the point just before unmuting all

drivers. At that point, the synchronization controller stalls,

waiting for the user to clear the appropriate manual sync bit.

This delay allows the user to update the Q divider ratios before

the controller unmutes the output drivers, which does not occur

until the user clears the relevant manual sync bit.

AUTORECONFIGURATION SYNC TRIGGER

An autoreconfiguration sync trigger occurs when the user

changes any of the Q divider ratios and subsequently sets the

IO_UPDATE bit. However, the autoreconfiguration sync trigger

applies only after the synchronization controller has already

completed a synchronization sequence as the result of a power-up

(or reset). After a power-up (or reset) synchronization sequence

completes, any subsequent updates to the Q divider ratios

constitutes an autoreconfiguration sync trigger.

Autoreconfiguration is a convenience feature, because it

synchronizes the outputs automatically when the user changes

one or more Q divider values and subsequently sets the

IO_UPDATE bit. This feature alleviates the need to initiate a

manual sync trigger to change Q divider values. Be aware,

however, that changing a single Q divider value affects all the

clock signals of the corresponding PLL channel. Specifically,

changing the value of any Q0X or Q0XX divider results in

disturbing all of the OUT0 clock outputs because it initiates a

synchronization sequence for those outputs. Likewise, changing

the value of any Q1X or Q1XX divider results in disturbing all of

the OUT1 clock outputs. These output clock disturbances are

unavoidable, because they result from the synchronization

process. The disturbances are, however, glitch free, because the

synchronization sequence mutes the affected output drivers

during synchronization.

The aforementioned output clock disturbances are avoidable,

however, when the enable SYSCLK to Qxy bits are set to Logic 1

and the enable SYSCLK sync mask bit are set to Logic 1 (see the

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