AD9545 datasheet(86/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 86 of 157

For example, suppose the users want to set the Profile x

frequency lock threshold bit field to meet the frequency

threshold when the signal from the reference TDC is 80 kHz

and the signal from the feedback TDC is 79.32 kHz (or vice versa).

Profile x Frequency Lock Threshold = |1/fREF

− 1/fFB|/10−12

= |1/80,000 − 1/79,320|/10−12

= 170,161 (nearest integer)

= 0x0298B1 (hexadecimal)

For more information on how to choose the appropriate

frequency lock threshold, fill rate and drain rate values for a

given application, refer to AN-1061 Application Note.

FREERUN TUNING WORD

The closed switch in Figure 71 indicates the DPLL is operating

in closed-loop mode, where the loop filter delivers FTWs in real

time to the NCO. In open-loop operation, the switch is open

and a static FTW processor provides the FTW to the NCO. The

loop controller opens or closes the switch as needed. For

example, when the DPLL is in freerun mode (that is, DPLLx

force freerun = 1 in Bit D0 of Register 0x2105 or Register

0x2205), the loop controller opens the switch and the FTW

processor routes the contents of the DPLLx freerun tuning word

bit field to the NCO.

In this case, the 46-bit unsigned DPLLx freerun tuning word bit

field (where x is 0 or 1) establishes the NCO output frequency.

The DPLLx freerun tuning word bit fields reside in Register 0x1000

to Register 0x1005 and Register 0x1400 to Register 0x1405.

fNCO

= fS × DPLLx Freerun TW/248

where:

fNCO is the NCO output frequency.

fS is the system clock frequency.

DPLLx Freerun TW represents the value of the 46-bit DPLLx

freerun tuning word bit field.

For example, assume a system clock frequency of 2.3 GHz and a

desired NCO output frequency of 245.76 MHz. Solving the fNCO

equation for DPLLx freerun TW yields the required value for

the DPLLx freerun tuning word bit field:

DPLLx Freerun TW = 248

× (fNCO/fS)

(21)

= 248 × (245.76 × 106/(2.3 × 109))

= 30,076,213,163,657 (nearest integer)

= 0x1B5AAA007689 (hexadecimal)

Although the tuning resolution of the NCO is 48 bits, the

DPLLx freerun tuning word bit field supports only 46 bits. The

reason is that, under all normal operating conditions, the two

most significant bits of the DPLLx freerun TW calculation (see

Equation 21) are always Logic 0. Therefore, the tuning word is 48

bits, but the DPLLx freerun tuning word bit field only uses the

rightmost 46 bits of the tuning word.

The value of DPLLx freerun tuning word must satisfy the

constraints imposed by the NCO SDM (see the DPLL NCO

section).

DPLL FAST ACQUISITION (FACQ) OPTIONS

FACQ Overview

Certain applications necessitate very low loop bandwidths. For

example, an application where the input reference to the DPLL

originates from a GPS/GNSS receiver with a 1 pulse per second

output. A 1 Hz reference requires a loop bandwidth much less

than 1 Hz, which can lead to very long frequency acquisition

and phase lock times in the range of minutes.

To overcome the long acquisition time imposed by a sub 1 Hz

loop bandwidth, the AD9545 provides a built-in fast acquisition

(FACQ) feature that greatly reduces the lock time of the DPLL.

The FACQ feature works by automatically changing the DPLL

loop filter bandwidth in a controlled manner. When the FACQ

feature is active (see the FACQ Bandwidth Control section) the

FACQ controller uses the following bit fields to control the fast

acquisition process (where x is the PLL channel (0 or 1) and y is

the profile number (0 to 5)):

•

Profile x.y loop bandwidth

•

Profile x.y fast acquisition excess bandwidth

•

Profile x.y fast acquisition lock settle time

•

Profile x.y fast acquisition timeout

These bit fields reside in Register 0x1200 to Register 0x12B7

and Register 0x1600 to Register 0x16B7.

The controller begins the fast acquisition process by applying a

user defined excess bandwidth factor to the bandwidth

specified by the Profile x.y loop bandwidth bit field. The

controller then successively reduces the excess bandwidth until

it reaches the bandwidth specified by the Profile x.y loop

bandwidth bit field. At each step in the bandwidth reduction

process, however, the controller waits for the DPLL phase

detector to indicate lock status before moving on to the next

step (see Figure 70).

FACQ Status Indicators

While the FACQ controller is in the process of performing a fast

acquisition, it sets the DPLLx FACQ active bit (where x is 0 or 1).

When the FACQ controller finishes the fast acquisition

procedure it sets the DPLLx FACQ done bit (where x is 0 or 1).

The user can query these bits to determine the state of the fast

acquisition controller. These bits reside in Bits[D5:D4] of

These bits relate to the IRQ function (see the Interrupt Request

(IRQ) section) per the DPLLx fast acquisition started and

DPLLx fast acquisition complete bits (where x is 0 or 1) in

Bits[D3:D2] of Register 0x3012 and Register 0x3017. Because

these IRQ bits are latched bits, the user must clear them via

Bits[D3:D2] of Register 0x200D and Register 0x2012 to obtain

visibility of subsequent state transitions of the FACQ controller.

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