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AD9545

Data Sheet

Rev. A | Page 88 of 157

FACQ Trigger

The preceding text describes the timing of the fast acquisition

process but not what triggers it. The user controls what triggers

the fast acquisition process per the following four bits that

reside in Bits[D3:D0] of Register 0x2106 and Register 0x2206:

•

Enable DPLLx fast acquisition from freerun

•

Enable DPLLx fast acquisition from holdover

•

Enable DPLLx fast acquisition first

•

Enable DPLLx fast acquisition no output

The FACQ controller treats the specific restrictions implied by

these bits in logical OR fashion. That is, the controller obeys all

the restrictions that apply per the set bits. Note that when all

four of these bits are Logic 0, no restrictions apply. That is, the

FACQ controller is completely unrestricted; the DPLL always

uses fast acquisition. However, making any one of these bits

Logic 1 puts the FACQ controller into a restricted operating

mode where it must obey the restrictions explicitly as follows.

Fast acquisition triggers under four sets of conditions.

•

When the enable DPLLx fast acquisition from freerun bit is

Logic 1 and the DPLL enters closed-loop operation from

freerun mode, fast acquisition triggers.

•

When the enable DPLLx fast acquisition from holdover bit

is Logic 1 and the DPLL enters closed-loop operation from

holdover mode, fast acquisition triggers

•

When the enable DPLLx fast acquisition first is Logic 1 and

this is the first execution of the fast acquisition process, fast

acquisition triggers. That is, the FACQ controller has not

completed a fast acquisition sequence previously (more

specifically, when the FACQ done bit is Logic 0). When the

FACQ done bit is Logic 1, the user can clear it by writing

Logic 1 to the autoclearing clear DPLLx fast acquisition

done bit in Bit D3 of Register 0x2107 or Register 0x2207.

This provides a mechanism to have subsequent first

acquisition events.

•

When the enable DPLLx fast acquisition no output is Logic 1,

and all the DPLLx clock distribution outputs are not

toggling, fast acquisition triggers.

As an example of FACQ trigger control, assume the enable

DPLLx fast acquisition from holdover and enable DPLLx fast

acquisition first bits are both Logic 1 and that DPLL enters

closed-loop operation from freerun mode, which does not

satisfy the first condition. However, because there is a second

restriction, and the device treats the restrictions in logical OR

fashion, the status of the second constraint applies. As such, if

the entry of the DPLL into closed-loop operation from freerun

mode happens to be the first acquisition in the DPLL, a fast

acquisition is in effect (otherwise, a normal acquisition results).

Next, assume the DPLL enters closed-loop operation from

holdover, which satisfies the first condition. As such, the DPLL

employs fast acquisition (the first acquisition restriction is

immaterial in this case).

DPLL PHASE OFFSET CONTROL

In general, the feedback loop of the DPLL (like the APLL) tends

to force the average phase offset between the two inputs of the

digital phase detector to zero (see Figure 74). As a result,

assuming integer-N operation (that is, the N-divider is not

fractional), the DPLL input and output signals are edge aligned

(or exhibit a constant time offset due to path latency).

The AD9545 DPLLs provide the ability to impose a programmable

time offset (tOFST) between the input and feedback signals by

means of a summing node at the feedback input of the digital

phase detector. To insert a time offset, use the 40-bit signed

DPLLx phase offset bit field (where x is 0 or 1), which has units

of picoseconds. The DPLLx phase offset bit fields reside in

Two other sources for applying a phase offset also feed the

summing node (not explicitly shown in Figure 74). One is via

the source profiles (see the Skew Adjustment section of the

Source Profiles section) and the other is via the delay

compensation feature (see the Delay Compensation sect ion).

DIGITAL

PHASE

DETECTOR

N-DIVIDER

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

DPLLx

PHASE OFFSET

NCO

LOCK

DETECTORS

FTW

PROCESSOR

DPLLx FREERUN

TUNING WORD

tOFST

–

LOOP

CONTROLLER

XOA XOB

AD9545

TDC

TEXT

= BIT(S) IN THE REGISTER MAP

48-BIT

FTW

DIGITAL

CROSS

POINT

MUX

Figure 74. DPLL Phase Offset Feature

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