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AD9545

Data Sheet

Rev. A | Page 74 of 157

The internal/external zero delay feedback path bit field value

relates to the Q divider output per the internal zero delay

column in Table 40. With DPLL N-divider set for integer only

(that is, no fractional component—a requirement for zero delay

operation), the internal zero delay configuration ensures no

phase offset between the reference TDC and the output of the

user-selected Q divider.

Table 40. Zero Delay Feedback Path Selection

Internal/

External Zero

Delay Feedback

Path Value

DPLL

Internal Zero

Delay

External Zero

Delay

OUT0AP

REFA

OUT0AP

REFA

OUT0AN

REFAA

OUT0AN

REFAA

OUT0BP

REFB

OUT0BP

REFB

OUT0BN

REFBB

OUT0BN

REFBB

OUT0CP

Not applicable

OUT0CC

Not applicable

6 to 31

n/a

Not applicable

The frequency translation factor for internal zero delay mode is

REFx

OUTx



To provide true hitless operation, internal zero delay mode

requires a constraint on the relationship between fREFx and fOUTx.

Namely, fOUTx/fREFx must be an integer greater than or equal to 1.

The NCO, VCO, TDCs, and the APLL PFD inputs each have

specific frequency limits. The following formulas relate fNCO,

fVCO, fTDC and fPFD to fREFx, fOUTx, and divider values. Note that

each formula has two solutions: one with respect to the input

frequency (fREFx) and the other with respect to the output

frequency (fOUTx). The user must ensure that fNCO, fVCO, fTDC, and

fPFD are within their specified frequency bounds.

fTDC = fREFx/R

= fOUTx/N

(8)

fNCO = fPFD = (2 × Q/M) × fOUTx

= ((2 × Q × N)/(R × M)) × fREFx

(9)

fVCO = 2 × Q × fOUTx

= (2 × Q × N/R) × fREFx

(10)

When the reference source is auxiliary NCO 0, auxiliary NCO 1,

or the feedback from the other DPLL, then in Equation 8

through Equation 10, use R = 1.

The DPLL provides the user with two status bits to indicate

when the DPLL transitions to or from hitless operation. The

DPLLx hitless entered bit (where x is 0 or 1) latches to Logic 1

when the DPLL enters hitless operating mode. The DPLLx

hitless exited bit (where x is 0 or 1) latches to Logic 1 when the

DPLL exits hitless operating mode. These bits reside in

Bits[D4:D3] of Register 0x3011 and Register 0x3016. Because

these are latched bits, the user must clear them via the IRQ map

DPLLx clear registers (Bits[D4:D3] of Register 0x200C and

transitions into and out of hitless operation.

Caveat to Internal Zero Delay Operation

Although the digital phase detector associated with the DPLL

can typically handle input frequencies as low as 1 Hz, the

internal zero delay mode imposes a lower boundary of 2 kHz on

the feedback input to the digital phase detector. The 2 kHz

lower bound applies only to the feedback input of the digital

phase detector, not to its reference input.

For internal zero delay operation in which the reference input

to the digital phase detector is less than 2 kHz, the user must

program the DPLL to use tagged feedback operation (see the

Time Stamp Tagging Options section in the Digital PLL (DPLL)

section). That is, for internal zero delay operation, the device

supports tagged feedback rates as low as 1 Hz whenthe

untagged feedback rate is greater than 2 kHz and fOUTx ≤ fNCO.

EXTERNAL ZERO DELAY (HITLESS) MODE

The external zero delay configuration appears in Figure 65.

External zero delay mode, like internal zero delay mode, is a

hitless operating mode (see the Internal Zero Delay (Hitless)

Mode section). As such, the same enter/exit hitless status bits

apply.

In external zero delay mode, the feedback path of the PLL is via

an external connection from an appropriate OUTx output to a

REFx input. The REFx input selection is via the 5-bit unsigned

internal/external zero delay feedback path bit field (per the

external zero delay column in Table 40). Typically, this feedback

path is merely a direct connection, but the external path may

also include an additional frequency translation component. To

discriminate between the normal and feedback reference inputs

in Figure 65, they appear as REFx and REFy, respectively.

The frequency translation factor from REFx to

OUTxyP/OUTxyN for external zero delay mode is:

OUTx

REFx

Rx Z



where Z is the external frequency translation factor such that

Z =

REFy

OUTx

To provide true hitless operation, external zero delay mode

requires a constraint on the relationship between fREFx and fREFy.

Namely, fREFy/fREFx must be an integer greater than or equal to 1.

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