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TMS320F28375DPZP Datasheet(PDF) 115 Page - Texas Instruments

Part # TMS320F28375DPZP
Description  TMS320F2837xD Dual-Core Delfino??Microcontrollers
PDF  222 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320F28375DPZP Datasheet(HTML) 115 Page - Texas Instruments

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CTRIPx = 0
0
CMPINxN or
DACxVAL
CTRIPx = 1
Hysteresis
COMPINxP
Voltage
CTRIPx
Logic Level
CTRIPx = 0
0
CMPINxN or
DACxVAL
CTRIPx = 1
Input Referred Offset
COMPINxP
Voltage
CTRIPx
Logic Level
115
TMS320F28379D, TMS320F28378D, TMS320F28377D
TMS320F28376D, TMS320F28375D, TMS320F28374D
www.ti.com
SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018
Submit Documentation Feedback
Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D
TMS320F28374D
Specifications
Copyright © 2013–2018, Texas Instruments Incorporated
5.10.2.1 CMPSS Electrical Data and Timing
Table 5-54 shows the comparator electrical characteristics. Figure 5-39 shows the CMPSS comparator
input referred offset. Figure 5-40 shows the CMPSS comparator hysteresis.
(1)
The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the CMPSS
DAC reference voltage. Hysteresis is available for all comparator input source configurations.
Table 5-54. Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power-up time (from COMPCTL[COMPDACE] to
comparator ready)
10
µs
Comparator input (CMPINxx) range
0
VDDA
V
Input referred offset error
–20
20
mV
Hysteresis(1)
1x
12
CMPSS
DAC LSB
2x
24
3x
36
4x
48
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Step response
21
60
ns
Ramp response (1.65 V/µs)
26
Ramp response (8.25 mV/µs)
30
NOTE
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If
a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal
comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V.
During this time, the internal comparator input will be floating and can decay below VDDA
within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect
result depending on the value of the other comparator input.
Figure 5-39. CMPSS Comparator Input Referred Offset
Figure 5-40. CMPSS Comparator Hysteresis



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