MCP47CMB02 datasheet(21/124 Pages) MICROCHIP

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DS20006089B-page 21

MCP47CXBXX

TABLE 1-5:

I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C AC Characteristics

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40

C  TA  +125C (Extended).

The operating voltage range is described in DC Characteristics.

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

103B(10)

TFSDA SDA Fall Time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz

mode)(4)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

160

3.4 MHz mode

106

THD:DAT Data Input Hold

Time

100 kHz mode

—

1.8V-5.5V(1,5)

400 kHz mode

—

2.7V-5.5V(5)

1.7 MHz mode

—

4.5V-5.5V(1,5)

3.4 MHz mode

—

4.5V-5.5V(1,5)

107

TSU:DAT Data Input Setup

Time

100 kHz mode

250

—

Notes 1, 6

400 kHz mode

100

—

Note 6

1.7 MHz mode

—

Notes 1, 6

3.4 MHz mode

—

Notes 1, 6

109

TAA

Output Valid from

Clock

100 kHz mode

—

3450

Notes 1, 5, 7, 9

400 kHz mode

—

900

Notes 5, 7, 9

1.7 MHz mode

—

310

Cb = 400 pF(1,9)

3.4 MHz mode

—

150

Cb = 100 pF(1,9)

110

TBUF Bus Free Time

100 kHz mode

4700

—

Time the bus must be free

before a new transmission

can start(1)

400 kHz mode

1300

—

1.7 MHz mode

N.A.

—

3.4 MHz mode

N.A.

—

111

TSP

Input Filter Spike

Suppression (SDA

and SCL)

100 kHz mode

—

NXP Spec states N.A.(1)

400 kHz mode

—

NXP Spec states N.A.

1.7 MHz mode

—

NXP Spec states N.A.(1)

3.4 MHz mode

—

NXP Spec states N.A.(1)

Note 1

Not tested. This parameter is ensured by characterization.

Note 4

Use Cb in pF for the calculations.

Note 5

A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does

not unintentionally create a Start or Stop condition.

Note 6

A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the

requirement, tSU:DAT  250 ns, must then be met. This will automatically be the case if the device does not

stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it

must output the next data bit to the SDA line, TR max.+ tSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I2C bus specification) before the SCL line is released.

Note 7

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Note 8

Ensured by the TAA 3.4 MHz specification test.

Note 9

The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

Note 10 Not tested. This parameter is ensured by design.

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