MCP47CMB02 datasheet(15/124 Pages) MICROCHIP

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DS20006089B-page 15

MCP47CXBXX

DC Notes:

This parameter is ensured by design.

This parameter is ensured by characterization.

POR/BOR voltage trip point is not slope-dependent. Hysteresis implemented with time delay.

Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = 10.

The PDxB:PDxA = 01, 10 and 11 configurations should have the same current.

Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = 10) to the VSS pin. For

dual channel devices (MCP47CXBX2), this is the effective resistance of each resistor ladder. The resistance

measurement is one of the two resistor ladders measured in parallel.

This gain error does not include the offset error.

Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit

device.)

Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.

10. Variation of one output voltage to mean output voltage for dual devices only.

11. High-voltage on the LAT/HVC pin must be limited to the command + programming time. After the programming

cycle, the LAT/HVC pin voltage must be returned to 5.5V or lower.

12. After 32 MTP write cycles, writes are inhibited and the 32nd write value is retained (not corrupted).

MCP47CMB02 Datasheet(PDF) 15 Page - Microchip Technology