MCP47CMB02 datasheet(66/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 66

 2018-2019 Microchip Technology Inc.

5.5

Power-Down Operation

To allow the application to conserve power when DAC

operation is not required, three Power-Down modes

are available. On devices with multiple DACs, each

DAC’s Power-Down mode is individually controllable.

All Power-Down modes do the following:

• Turn off most of the DAC module’s internal circuits

• Op amp output becomes high-impedance to the

VOUT pin

• Retain the value of the Volatile DAC register and

Configuration bits

Depending on the selected Power-Down mode, the

following will occur:

•VOUT pin is switched to one of the two resistive

pull-downs:

-100 k

 (typical)

-1 k

 (typical)

• Op amp is powered down and the VOUT pin

becomes high-impedance

The Power-Down Configuration bits (PD1:PD0) control

the power-down operation (Table 5-4).

TABLE 5-4:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

There is a delay (TPDD) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the

op amp no longer driving the VOUT output, and the

pull-down resistors’ sinking current.

In any of the Power-Down modes, where the VOUT pin

is not externally connected (sinking or sourcing cur-

rent), as the number of DACs increases, the device’s

power-down current will also increase.

Table 5-5 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in normal operating mode or one of

the Power-Down modes.

The power-down bits are modified by using a write

command to the Volatile Power-Down register, or a POR

event, which transfers the Nonvolatile Power-Down

Section 7.0 “Device Commands” describes the I2C

commands for writing the power-down bits. The

commands that can update the volatile PD1:PD0 bits are:

•Write

• General Call Reset

• General Call Wake-up

5.5.1

EXITING POWER-DOWN

The following events change the PD1:PD0 bits to ‘00’,

and therefore, exit the Power-Down mode. These are:

•Any I2C Write Command, where the PD1:PD0 bits

are ‘00’

•I2C General Call Wake-up Command

•I2C General Call Reset Command

When the device exits Power-Down mode, the

following occurs:

• Disabled internal circuits are turned on

• Resistor ladder is connected to the selected

Reference Voltage (VRL)

• Selected pull-down resistor is disconnected

•The VOUT output is driven to the voltage

represented by the Volatile DAC register’s value

and Configuration bits

The DAC Wiper register and DAC wiper value may be

different due to the DAC Wiper register being modified

while the LAT pin was driven to (and remaining at) VIH.

The VOUT output signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value, as determined by the Volatile DAC

PD1

PD0

Function

Normal operation

 resistor to ground

100 k

 resistor to ground

Open circuit

TABLE 5-5:

DAC CURRENT SOURCES

Device VDD Current

Source

PDxB:xA = 00,

VREFxB:xA =

PDxB:xA

 00,

VREFxB:xA =

00 01 10

01 10 11

Output Op Amp

Resistor Ladder

Y N(1)

N N(1) N

VREF Selection Buffer N

Band Gap

N(2) Y(2) N(2) N(2)

Note 1: The current is sourced from the VREF pin, not the

device VDD.

2: If DAC0 and DAC1 are in one of the Power-Down

modes, MTP write operations are not recommended.

Note 1: The I2C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I2C Master device.

2: A General Call Reset will do the POR

event sequence, except that the MTP

shadow memory values will be transfered

to the Volatile Memory registers.

Note:

Since the op amp and resistor ladder were

powered off (0V), the op amp’s Input

Voltage (VW) can be considered as 0V.

There is a delay (TPDE) between the

PD1:PD0 bits updating to ‘00’ and the

op amp driving the VOUT output. The

op amp’s settling time (from 0V) needs to

be taken into account to ensure the VOUT

voltage reflects the selected value.

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