MCP47CMB02 datasheet(62/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 62

 2018-2019 Microchip Technology Inc.

5.2.3

USING AN EXTERNAL VREF

SOURCE IN BUFFERED MODE

The VREF pin voltage may be from 0V to VDD. The input

buffer (amplifier) provides low offset voltage, low noise,

and a very high input impedance, with only minor

limitations on the input range and frequency response.

Any variation or noises on the reference source can

directly affect the DAC output. The reference voltage

needs to be as clean as possible for accurate DAC

performance.

5.2.4

USING THE INTERNAL BAND GAP

AS VOLTAGE REFERENCE

The internal band gap is designed to drive the resistor

ladder buffer.

If the internal band gap is selected, then the band gap

voltage source will drive the external VREF pins. The

VREF0 pin can source up to 1 mA of current without

affecting the DAC output specifications. The VREF1 pin

must be left unloaded in this mode. The voltage refer-

ence source can be independently selected on devices

with two DAC channels, but restrictions apply:

•The VDD mode can be used without issues on any

channel.

• When the internal band gap is selected as the voltage

source, all the VREF pins are connected to its output.

The use of the Unbuffered mode is only possible on

VREF0, because it’s the only one that can be loaded.

• When using the Internal Band Gap mode on

Channel 0, Channel 1 must be put in Buffered

External VREF mode or VDD Reference mode and

the VREF1 pin must be left unloaded.

The resistance of the Resistor Ladder (RRL) is targeted

to be 71 k

 (10%), which means a minimum

resistance of 63.9 k

.

The band gap selection can be used across the VDD

voltages while maximizing the VOUT voltage ranges.

For VDD voltages below the Gain  VBG voltage, the

output for the upper codes will be clipped to the VDD

voltage. Table 5-1 shows the maximum DAC register

code given device VDD and Gain bit setting.

5.3

Output Buffer/VOUT Operation

The output driver buffers the Wiper Voltage (VW) of the

resistor ladder.

The DAC output is buffered with a low-power, precision

output amplifier with selectable gain. This amplifier pro-

vides a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high-capacitive loads without oscillation. The amplifier

provides a maximum load current, which is enough for

most programmable voltage reference applications.

Refer to Section 1.0 “Electrical Characteristics” for

the specifications of the output amplifier.

Figure 5-5 shows a block diagram of the output driver

circuit.

FIGURE 5-5:

Output Driver Block Diagram.

Power-down logic also controls the output buffer

operation (see Section 5.5 “Power-Down Operation”

for additional information on power-down). In any of the

three Power-Down modes, the output amplifier is

powered down and its output becomes a high-impedance

to the VOUT pin.

5.3.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-4) and the VRL

reference selection (see Register 4-2).

The Gain options are:

a) Gain of 1, with either the VDD or VREF pin used

as the reference voltage.

b) Gain of 2, only when the VREF pin or the internal

band gap is used as the reference voltage. The

VREF pin voltage should be limited to VDD/2.

When the Reference Voltage Selection (VRL) is

the device’s VDD voltage, the Gx bit is ignored

and a gain of 1 is used.

TABLE 5-1:

VOUT USING BAND GAP

Max DAC Code(1)

Comment

12-Bit 10-Bit 8-Bit

5.5

FFFh

3FFh

FFh VOUT(max) = 1.214V

(3)

FFFh

3FFh

FFh VOUT(max) = 2.428V

(3)

2.7

FFFh

3FFh

FFh VOUT(max) = 1.214V

(3)

FFFh

3FFh

FFh VOUT(max) = 2.428V

1.8

FFFh

3FFh

FFh VOUT(max) = 1.214V

2(2) BBCh2EFhBBh 1.8V

Note 1: Without the VOUT pin voltage being clipped.

2: Recommended to use the Gain = 1 setting.

3: When VBG = 1.214V typical.

Note:

The load resistance must be kept higher

than 2 k

 to maintain stability of the

analog output and have it meet electrical

specifications.

VOUT

PD1:PD0

VDD

PD1:PD0

Gain

(1x or 2x)

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