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MCP47CMB02 Datasheet(PDF) 56 Page - Microchip Technology |
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MCP47CMB02 Datasheet(HTML) 56 Page - Microchip Technology |
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56 / 124 page  MCP47CXBXX DS20006089B-page 56 2018-2019 Microchip Technology Inc. Register 4-4 shows the format of the Gain Control and System Status register. Each DAC has one bit to control the gain of the DAC and two Status bits. REGISTER 4-4: GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah) (VOLATILE) U-0 U-0 U-0 U-0 U-0 U-0 R/W-n R/W-n R/C-1 R U-0 U-0 U-0 U-0 U-0 U-0 Single — —— —— — —(1) G0 POR MTPMA — —— ——— Dual — — — — — — G1 G0 POR MTPMA — — — — — — bit 15 bit 0 Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown = Single channel device = Dual channel device Single Dual bit 15-9 bit 15-10 Unimplemented: Read as ‘0’ — bit 9 G1: DAC1 Output Driver Gain Control bit 1 = 2x gain; not applicable when VDD is used as VRL (2) 0 =1x gain bit 8 bit 8 G0: DAC0 Output Driver Gain Control bit 1 = 2x gain; not applicable when VDD is used as VRL (2) 0 = 1x gain bit 7 bit 7 POR: Power-on Reset (Brown-out Reset) Status bit This bit indicates if a POR or BOR event has occurred since the last read command of this register. Reading this register clears the state of the POR Status bit. 1 = A POR (BOR) event occurred since the last read of this register; reading this register clears this bit 0 = A POR (BOR) event has not occurred since the last read of this register bit 6 bit 6 MTPMA: MTP Memory Access Status bit(3) This bit indicates if the MTP memory access is occurring. 1 = An MTP memory access is currently occurring (during the POR MTP read cycle or an MTP write cycle is occurring); only serial commands addressing the volatile memory are allowed 0 = An MTP memory access is NOT currently occurring bit 5-0 bit 5-0 Unimplemented: Read as ‘0’ Note 1: Unimplemented bit, read as ‘0’. 2: The DAC’s Gain bit is ignored and the gain is forced to 1x (Gx = 0) when the DAC voltage reference is selected as VDD (VRxB:VRxA = 00). 3: For devices configured as volatile memory, this bit is read as ‘0’. |
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