MCP47CMB02 datasheet(86/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 86

 2018-2019 Microchip Technology Inc.

8.2

Power Supply Considerations

The power source should be as clean as possible. The

power supply to the device is also used for the DAC

voltage reference internally if the internal VDD is

selected as the resistor ladder’s reference voltage

(VRxB:VRxA = 00).

Any noise induced on the VDD line can affect the DAC

performance. Typical applications will require a bypass

capacitor in order to filter out high-frequency noise on

the VDD line. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC out-

put. The bypass capacitor helps to minimize the effect of

these noise sources on signal integrity. Figure 8-2

shows an example of using two bypass capacitors (a

10 µF tantalum capacitor and a 0.1 µF ceramic capaci-

tor) in parallel on the VDD line. These capacitors should

be placed as close to the VDD pin as possible (within

4 mm). If the application circuit has separate digital and

analog power supplies, the VDD and VSS pins of the

device should reside on the analog plane.

FIGURE 8-2:

Example Circuit.

Analog

VDD

SDA

SCL

VSS

VOUT0

To MCU

R1 and R2 are I2C pull-up resistors:

R1 and R2:

-10 k for fSCL = 100 kHz to 400 kHz

~700

 for fSCL = 3.4 MHz

C1: 0.1 µF capacitor

= Ceramic

C2: 10 µF capacitor

= Tantalum

C3:~ 0.1 µF

= Optional to reduce noise in

VOUT pin

C4: 0.1 µF capacitor

= Ceramic

C5: 10 µF capacitor

= Tantalum

C6: 0.1 µF capacitor

= Ceramic

MCP47CVBX2

Optional

(a) Circuit when VDD is selected as reference.

Note: VDD is connected to the reference circuit internally.

(b) Circuit when external reference is used.

Output

VREF

LAT/HVC

VOUT1

Analog

VDD

SDA

SCL

VSS

VOUT0

To MCU

MCP47CVBX2

Optional

Output

VREF

LAT/HVC

VOUT1

Optional

VREF

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