MCP47CMB02 datasheet(64/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 64

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5.3.4

OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate of the VOUT

pin. The slew rate can be affected by the characteristics

of the circuit connected to the VOUT pin.

FIGURE 5-6:

VOUT Pin Slew Rate.

5.3.4.1

Small Capacitive Load

With a small capacitive load, the output buffer’s current

is not affected by the Capacitive Load (CL). But still, the

VOUT pin’s voltage is not a step transition from one out-

put value (DAC register value) to the next output value.

The change of the VOUT voltage is limited by the output

buffer’s characteristics, so the VOUT pin voltage will

have a slope from the old voltage to the new voltage.

This slope is fixed for the output buffer, and is referred

to as the Buffer Slew Rate (SRBUF).

5.3.4.2

Large Capacitive Load

With a larger capacitive load, the slew rate is

determined by two factors:

• The output buffer’s Short-Circuit Current (ISC)

•The VOUT pin’s external load

IOUT cannot exceed the output buffer’s Short-Circuit

Current (ISC), which fixes the output Buffer Slew Rate

(SRBUF). The voltage on the Capacitive Load (CL), VCL,

changes at a rate proportional to IOUT, which fixes a

Capacitive Load Slew Rate (SRCL).

The VCL voltage slew rate is limited to the slower of the

output buffer’s internally Set Slew Rate (SRBUF) and

the Capacitive Load Slew Rate (SRCL).

5.3.5

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive load

in parallel with a 5 k

 resistive load (to meet electrical

specifications). VOUT drops slowly as the load resis-

tance decreases after about 3.5 k

. It is recommended

to use a load with RL greater than 2 k.

Refer to Section 2.0 “Typical Performance Curves” for

a detailed VOUT vs. Resistive Load characterization

graph.

Driving large capacitive loads can cause stability

problems for voltage feedback output amplifiers. As the

load capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the VOUT pin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

VOUT pin.

So, when driving large capacitive loads with the output

buffer, a small Series Resistor (RISO) at the output (see

Figure 5-7) improves the output buffer’s stability

(feedback loop’s phase margin) by making the output

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

FIGURE 5-7:

Circuit to Stabilize Output

Buffer for Large Capacitive Loads (CL).

The RISO resistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this RISO resistor

value should be verified on the bench. Modify the

RISO’s resistance value until the output characteristics

meet your requirements.

A method to evaluate the system’s performance is to

inject a step voltage on the VREF pin and observe the

VOUT pin’s characteristics.

Time

DACx = A

VOUT(A)

VOUT(B)

DACx = B

Slew Rate

VOUT B



VOUT A



–

T

--------------------------------------------------

Note:

Additional insight into circuit design for

driving capacitive loads can be found in

AN884, “Driving Capacitive Loads With

Op Amps” (DS00884).

Gain

VOUT

RISO

VCL

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