MCP47CMB02 datasheet(71/124 Pages) MICROCHIP

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DS20006089B-page 71

MCP47CXBXX

6.10

Entering High-Speed (HS) Mode

The I2C specification requires that a High-Speed mode

device be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The Master code is sent as follows:

Start condition (S).

High-Speed Master Mode Code (‘0000 1xxx’);

the ‘xxx’ bits are unique to the High-Speed (HS)

Master mode.

No Acknowledge (A).

After switching to High-Speed mode, the next trans-

ferred byte is the I2C control byte, which specifies the

device to communicate with and any number of data

bytes plus Acknowledgments. The Master device can

then either issue a Repeated Start bit to address a

different device (at High-Speed mode) or a Stop bit to

return to the bus Fast/Standard Speed mode. After the

Stop bit, any other Master device (in a Multi-Master

system) can arbitrate for the I2C bus.

The MCP47CXBXX device does not Acknowledge the

HS select byte. However, upon receiving this

command, the device switches to HS mode.

See Figure 6-3 for an illustration of the HS mode

command sequence.

For more information on the HS mode, or other I2C

modes, refer to the “NXP I2C Specification”.

FIGURE 6-3:

HS Mode Sequence.

‘0000 1xxx’b’

Slave Address

A/A

Data

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS mode)

F/S Mode

HS Mode

HS Mode Continues

F/S Mode

Slave Address R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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