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MCP47CMB02 Datasheet(PDF) 52 Page - Microchip Technology |
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MCP47CMB02 Datasheet(HTML) 52 Page - Microchip Technology |
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52 / 124 page ![]() MCP47CXBXX DS20006089B-page 52 2018-2019 Microchip Technology Inc. TABLE 4-2: FACTORY DEFAULT POR/BOR VALUES (MTP MEMORY UNPROGRAMMED) Function POR/BOR Value Function POR/BOR Value 00h Volatile DAC0 Register 7Fh 1FFh 7FFh 10h Nonvolatile DAC0 Wiper Register(1) 7Fh 1FFh 7FFh 01h Volatile DAC1 Register 7Fh 1FFh 7FFh 11h Nonvolatile DAC1 Wiper Register(1) 7Fh 1FFh 7FFh 02h Reserved(3) — — — 12h Reserved(3) — — — 03h Reserved(3) — — — 13h Reserved(3) — — — 04h Reserved(3) — — — 14h Reserved(3) — — — 05h Reserved(3) — — — 15h Reserved(3) — — — 06h Reserved(3) — — — 16h Reserved(3) — — — 07h Reserved(3) — — — 17h Reserved(3) — — — 08h Volatile VREF Register 0000h 0000h 0000h 18h Nonvolatile VREF Register(1) 0000h 0000h 0000h 09h Volatile Power-Down Register 0000h 0000h 0000h 19h Nonvolatile Power-Down Register(1) 0000h 0000h 0000h 0Ah Volatile Gain and Status Register(4) 0080h 0080h 0080h 1Ah NV Gain and I2C 7-Bit Slave Address(1,2) 0060h 0060h 0060h 0Bh Reserved(3) 0000h 0000h 0000h 1Bh NV WiperLock™ Technology Register(1) 0000h 0000h 0000h 0Ch General Purpose MTP(1) 0000h 0000h 0000h 1Ch General Purpose MTP(1) 0000h 0000h 0000h 0Dh General Purpose MTP(1) 0000h 0000h 0000h 1Dh General Purpose MTP(1) 0000h 0000h 0000h 0Eh General Purpose MTP(1) 0000h 0000h 0000h 1Eh General Purpose MTP(1) 0000h 0000h 0000h 0Fh General Purpose MTP(1) 0000h 0000h 0000h 1Fh General Purpose MTP(1) 0000h 0000h 0000h Legend: Volatile Memory Address Range Nonvolatile Memory Address Range Not Implemented Note 1: On nonvolatile devices only (MCP47CMBXX). 2: Default I2C 7-bit Slave address is ‘110 0000’ (‘110 00xx’ when A1:A0 bits are determined from the A1 and A0 pins). 3: Reading a reserved memory location will result in the I2C command to Not ACK the command byte. The device data bits will output all ‘1’s. A Start condition will reset the I2C interface. 4: The ‘1’ bit is the POR status bit, which is set after the POR event and cleared after address 0Ah is read. |
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