MCP47CMB02 datasheet(78/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 78

 2018-2019 Microchip Technology Inc.

7.6

Read Command

Read commands are used to transfer data from the

specified memory location to the Host controller.

The read command can be issued to both the volatile

and nonvolatile memory locations. During an MTP

memory write cycle, the read command can only read

the volatile memory locations. By reading the Status

when the Write Cycle (twc) has been completed (via

the state of the MTPMA bit).

The read command formats include:

• Single Read

- Single Memory Address

- Last Memory Address Accessed

• Continuous Reads

The MCP47CXBXX retains the last received device

memory address. This means the MCP47CXBXX does

not corrupt the device memory address after Repeated

Start or Stop conditions.

7.6.1

SINGLE READ

The read command format writes two bytes, the control

byte and the read command byte (desired memory

address and the read command), and then has a

Restart condition. Then, a second control byte is

transmitted, but this control byte indicates an I2C read

operation (R/W bit = 1).

7.6.1.1

Single Memory Address

Figure 7-4 shows the sequence for reading a specified

memory address.

7.6.1.2

Last Memory Address Accessed

This is useful for checking the status of the MTPMA bit

or when writes to other I2C devices on the bus must

occur between these memory reads. The Master must

send a Stop or Restart condition after the data word is

sent from the Slave. Figure 7-5 shows the waveforms

for a single read of the last memory location accessed.

7.6.2

CONTINUOUS READS

Continuous reads allow the device’s memory to be

read quickly and are valid for all memory locations.

Figure 7-7 shows the sequence for three continuous

reads.

For continuous reads, instead of transmitting a Stop or

Restart condition after the data transfer, the Master

continually reads the data byte. The sequence ends

with the Master Not Acknowledging and then sending a

Stop or Restart.

7.6.3

IGNORING AN I2C TRANSMISSION

AND “FALLING OFF” THE BUS

The MCP47CXBXX expects to receive complete, valid

I2C commands and will assume any command not

defined as a valid command is due to a bus corruption,

thus entering a passive high condition on the SDA

signal. All signals will be ignored until the next valid

Start condition and control byte are received.

Note 1: During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP47CXBXX will NACK

that byte. To reset the I2C state machine,

the I2C communication must detect a

Start bit.

2: If the LAT pin is high (VIH), reads of the

Volatile DAC register return the current

output value, not the internal register

value.

3: The read commands operate the same

regardless of the state of the High-Voltage

Command (HVC) signal.

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