MCP47CMB02 datasheet(69/124 Pages) MICROCHIP

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DS20006089B-page 69

MCP47CXBXX

6.0

I2C SERIAL INTERFACE

MODULE

The MCP47CXBXX’s I2C serial interface module

supports the I2C serial protocol specification. This I2C

interface is a two-wire interface (clock and data).

Figure 6-1 shows a typical I2C interface connection.

The I2C specification only defines the field types,

lengths, timings, etc., of a frame. The frame content

defines the behavior of the device. The frame content

(commands) for the MCP47CXBXX is defined in

Section 7.0 “Device Commands”.

An overview of the I2C protocol is available in

Appendix B: “I2C Serial Interface”.

FIGURE 6-1:

Typical I2C Interface.

6.1

Overview

This section discusses some of the specific character-

istics of the MCP47CXBXX devices’ I2C serial interface

module. This is to assist in the development of your

application.

The following sections discuss some of these

device-specific characteristics.

• Interface Pins (SCL and SDA)

• Communication Data Rates

• POR/BOR

• Device Memory Address

• General Call Commands

• Device I2C Slave Addressing

• Slope Control

6.1.1

INTERFACE PINS (SCL AND SDA)

The MCP47CXBXX I2C module SCL pin does not

generate the serial clock since the device operates in

Slave mode. Also, the MCP47CXBXX will not stretch

the clock signal (SCL) since memory read access

occurs fast enough.

The MCP47CXBXX I2C module implements slope

control on the SDA pin output driver.

6.2

Communication Data Rates

The I2C interface specifies different communication bit

rates. These are referred to as Standard, Fast or High-

Speed modes. The MCP47CXBXX supports these

three modes. The clock rates (bit rate) of these modes

are:

• Standard mode: Up to 100 kHz (kbit/s)

• Fast mode: Up to 400 kHz (kbit/s)

• High-Speed mode (HS mode): Up to 3.4 MHz

(Mbit/s)

A description on how to enter High-Speed mode is

described in Section 6.8 “Slope Control”.

6.3

POR/BOR

On a POR/BOR event, the I2C serial interface module

state machine is reset, which includes forcing the

device’s Memory Address Pointer to 00h.

6.4

Device Memory Address

The memory address is the 5-bit value that specifies

the location in the device’s memory that the specified

command will operate on.

On a POR/BOR event, the device’s Memory Address

Pointer is forced to 00h.

The MCP47CXBXX retains the last received “Device

Memory Address”. That is, the MCP47CXBXX does not

“corrupt” the “device memory address” after Repeated

Start or Stop conditions.

6.5

General Call Commands

The general call commands utilize the I2C specification

reserved general call command address and command

codes. The MCP47CXBXX also implements a

nonstandard general call command.

The general call commands are:

• General Call Reset

• General Call Wake-up (MCP47CXBXX defined)

The general call wake-up command will cause all the

MCP47CXBXX devices to exit their power-down state.

6.6

Multi-Master Systems

The MCP47CXBXX is not a Master device (generates

the interface clock), but it can be used in Multi-Master

applications.

SCL

MCP47CVBXX

SDA

Host

Controller

Typical I2C Interface Connections

Other Devices

(Master)

(Slave)

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