MCP47CMB02 datasheet(47/124 Pages) MICROCHIP

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DS20006089B-page 47

MCP47CXBXX

4.0

GENERAL DESCRIPTION

The MCP47CXBX1 (MCP47CXB01, MCP47CXB11

and MCP47CXB21) devices are single-channel voltage

output devices.

MCP47CXBX2 (MCP47CXB02, MCP47CXB12 and

MCP47CXB22) are dual channel voltage output devices.

These devices are offered with 8-bit (MCP47CXB0X),

10-bit (MCP47CXB1X) and 12-bit (MCP47CXB2X)

resolutions.

The family offers two memory options: the

MCP47CVBXX devices have volatile memory, while

the MCP47CMBXX have 32-times programmable

nonvolatile memory (MTP).

All devices include an I2C serial interface and a write

latch (LAT) pin to control the update of the analog out-

put voltage value from the value written in the Volatile

DAC Output register.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal VDD, an external VREF

pin voltage (buffered or unbuffered) or an internal

band gap voltage source.

The DAC output is buffered with a low-power and

precision output amplifier. This output amplifier pro-

vides a rail-to-rail output with low offset voltage and

low noise. The gain (1x or 2x) of the output buffer is

software configurable.

The devices operate from a single supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation, and from 1.8V to 5.5V for digital operation.

The device operates between 1.8V and 2.7V, but

some device parameters are not specified.

The

MCP47CMBXX

devices

also

have

user-

programmable

nonvolatile

configuration

memory

(MTP). This allows the device’s desired POR values to

be saved or the I2C address to be changed. The

device also has general purpose MTP memory

locations for storing system-specific information

(calibration data, serial numbers, system ID informa-

tion). A high-voltage requirement for programming on

the HVC pin ensures that these device settings are not

accidentally modified during normal system operation.

Therefore, it is recommended that the MTP memory

should only be programmed at the user’s factory.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/VOUT Operation

• I2C Serial Interface Module

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

The internal Power-on Reset (POR)/Brown-out Reset

(BOR) circuit monitors the power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

The device’s RAM Retention Voltage (VRAM) is lower

than the POR/BOR Voltage Trip Point (VPOR/VBOR).

The maximum VPOR/VBOR voltage is less than 1.8V.

The POR and BOR trip points are at the same voltage,

and the condition is determined by whether the VDD

voltage is rising or falling (see Figure 4-1). What occurs

is different depending on whether the Reset is a POR

or BOR Reset.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

VDD(MIN) or higher).

When VPOR/VBOR < VDD < 2.7V, the electrical perfor-

mance may not meet the data sheet specifications. In

this region, the device is capable of reading and writing

to its volatile memory if the proper serial command is

executed.

4.1.1

POWER-ON RESET

The Power-on Reset is the case where the device’s

VDD has power applied to it from the VSS voltage level.

As the device powers up, the VOUT pin floats to an

unknown value. When the device’s VDD is above the

transistor threshold voltage of the device, the output

starts to be pulled low.

After the VDD is above the POR/BOR trip point

(VBOR/VPOR), the resistor network’s wiper is loaded

with the POR value. The POR value is either mid-scale

(MCP47CVBXX) or the user’s MTP programmed value

(MCP47CMBXX).

Note:

In order to have the MCP47CMBXX

devices load the values from nonvolatile

memory locations at POR, they have to be

programmed at least once by the user;

otherwise, the loaded values will be the

default ones. After MTP programming, a

POR event is required to load the written

values from the nonvolatile memory.

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