MCP47CMB02 datasheet(91/124 Pages) MICROCHIP

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DS20006089B-page 91

MCP47CXBXX

8.9

Software I2C Interface Reset

Sequence

At times, it may become necessary to perform a

Software Reset sequence to ensure the MCP47CXBXX

device is in a correct and known I2C interface state. This

technique only resets the I2C state machine.

This is useful if the MCP47CXBXX device powers up in

an incorrect state (due to excessive bus noise, etc.), or

if the Master device is reset during communication.

Figure 8-9 shows the communication sequence to

software reset the device.

FIGURE 8-9:

Software Reset Sequence

Format.

The first Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master device. In this mode, the device is monitoring

the data bus in Receive mode and can detect if the

Start bit forces an internal Reset.

The nine bits of ‘1’ are used to force a reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47CXBXX is driving an A bit

on the I2C bus or is in Output mode (from a read

command) and is driving a data bit of ‘0’ onto the I2C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP47CXBXX holding the

bus low. By sending out nine ‘1’ bits, it is ensured that the

device will see an A bit (the Master device does not drive

the I2C bus low to Acknowledge the data sent by the

MCP47CXBXX), which also forces the MCP47CXBXX to

reset.

The second Start bit is sent to address the rare

possibility of an erroneous write. This could occur if the

Master device was reset while sending a write com-

mand to the MCP47CXBXX, and then as the Master

device returns to normal operation and issues a Start

condition, while the MCP47CXBXX is issuing an

Acknowledge. In this case, if the second Start bit is not

sent (and the Stop bit was sent), the MCP47CXBXX

could initiate a write cycle.

The Stop bit terminates the current I2C bus activity. The

MCP47CXBXX waits to detect the next Start condition.

This sequence does not affect any other I2C devices

which may be on the bus, as they should disregard this

as an invalid command.

8.10

Design Considerations

In the design of a system with the MCP47CXBXX

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

8.10.1

POWER SUPPLY

CONSIDERATIONS

The typical application requires a bypass capacitor in

order to filter high-frequency noise, which can be

induced onto the power supply’s traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-10 illustrates an

appropriate bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as close

(within 4 mm) to the device power pin (VDD) as possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 8-10:

Typical Microcontroller

Connections.

Note:

This technique is documented in AN1028,

“Recommended Usage of Microchip I2C

Serial EEPROM Devices” (DS01028).

Note:

The potential for this erroneous write

ONLY occurs if the Master device is reset

while sending a write command to the

MCP47CVBXX.

S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’ S

Start

Nine Bits of ‘1’

Start Bit

Stop Bit

Bit

VDD

VSS

0.1 µF

SCL

VOUT

VREF

SDA

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