68HC705JB4 datasheet(32/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

INTERRUPTS

MC68HC05JB4

4-2

REV 2

NOTE

If more than one interrupt request is pending, the CPU fetches the vector of the

higher priority interrupt ﬁrst. A higher priority interrupt does not actually interrupt a

lower priority interrupt service routine unless the lower priority interrupt service

routine clears the I bit.

4.2

INTERRUPT PROCESSING

The CPU does the following actions to begin servicing an interrupt:

•

Stores the CPU registers on the stack in the order shown in Figure 4-1.

•

Sets the I bit in the condition code register to prevent further interrupts.

•

Loads the program counter with the contents of the appropriate interrupt

vector locations as shown in Table 4-1.

The return from interrupt (RTI) instruction causes the CPU to recover its register

contents from the stack as shown in Figure 4-1. The sequence of events caused

by an interrupt are shown in the ﬂow chart in Figure 4-2.

$0020

(BOTTOM OF RAM)

$0021

$00BE

$00BF

$00C0

(BOTTOM OF STACK)

$00C1

$00C2

UNSTACKING

ORDER

⇓

CONDITION CODE REGISTER

n+1

ACCUMULATOR

n+2

INDEX REGISTER

n+3

PROGRAM COUNTER (HIGH BYTE)

n+4

PROGRAM COUNTER (LOW BYTE)

⇑

STACKING

$00FD

ORDER

$00FE

$00FF

TOP OF STACK (RAM)

Figure 4-1. Interrupt Stacking Order

Freescale Semiconductor, Inc.

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