68HC705JB4 datasheet(45/134 Pages) FREESCALE

45 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

LOW POWER MODES

MOTOROLA

REV 2

6-3

6.1

STOP MODE

STOP mode is entered by executing the STOP instruction. This is the lowest

power consumption mode of the MCU. In the STOP Mode the internal oscillator is

turned off, halting all internal processing.

Execution of the STOP instruction automatically clears the I-bit in the Condition

Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so

that the IRQ external interrupt is enabled. All other registers, including the other

bits in the TCSR, and memory remain unaltered. All input/output lines remain

unchanged.

The MCU can be brought out of the STOP Mode by an IRQ external interrupt,

IRQ2 external interrupt or a USB coming out from Suspend Mode Interrupt (Bus

activity detection) or an externally generated RESET, USB Reset or an LVR reset.

When exiting the STOP Mode the internal oscillator will resume after a 128 or

4064 internal processor clock cycle oscillator stabilization delay.

6.2

WAIT MODE

WAIT mode is entered by executing the WAIT instruction. This places the MCU in

a low-power mode, which consumes more power than the STOP Mode. In the

WAIT Mode the internal processor clock is halted, suspending all processor and

internal bus activity. Execution of the WAIT instruction automatically clears the I-bit

in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/

Status Register so that the IRQ external interrupt is enabled. All other registers,

memory, and input/output lines remain in their previous states.

The WAIT Mode may be exited when an external IRQ, IRQ2, USB, Timer1 or MFT

interrupt, an LVR reset, USB reset or an external RESET occurs.

6.3

DATA-RETENTION MODE

The Data-Retention mode is only available if the Low Voltage Reset function

(mask option) is not enabled.

In the data retention mode, the MCU retains RAM contents and CPU register con-

tents at VDD voltages as low as 2.0Vdc. The data retention feature allows the

MCU to remain in a low power consumption state during which it retains data, but

the CPU cannot execute instructions. The RESET pin must be held low during

data-retention mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705JB4 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc

68HC705JB4 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL