68HC705JB4 datasheet(64/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

16-BIT TIMER

MC68HC05JB4

9-8

REV 2

A software example of this procedure is shown below.

9.5

TIMER CONTROL REGISTER (TCR)

The timer control register is shown in Figure 9-10 performs the following func-

tions:

•

Enables input capture interrupts

•

Enables output compare interrupts

•

Enables timer overﬂow interrupts

•

Control the active edge polarity of the ICAP1 signal on pin PB0/ICAP1

Reset clears all the bits in the TCR with the exception of the IEDG bit which is

unaffected.

ICIE - INPUT CAPTURE INTERRUPT ENABLE

This read/write bit enables interrupts caused by an active signal on the PB0/

ICAP1 pin. Reset clears the ICIE bit.

1 =

Input capture interrupts enabled.

0 =

Input capture interrupts disabled.

OCIE - OUTPUT COMPARE INTERRUPT ENABLE

This read/write bit enables interrupts caused by a successful compare between

the timer counter and the output compare registers. Reset clears the OCIE bit.

1 =

Output compare interrupts enabled.

0 =

Output compare interrupts disabled.

TOIE - TIMER OVERFLOW INTERRUPT ENABLE

This read/write bit enables interrupts caused by a timer overﬂow. Reset clears

the TOIE bit.

1 =

Timer overﬂow interrupts enabled.

0 =

Timer overﬂow interrupts disabled.

...

SEI

...

STA

LDA

STX

...

CLI

OCRH

TSR

OCRL

DISABLE INTERRUPTS

.....

INHIBIT OUTPUT COMPARE

ARM OCF FLAG FOR CLEARING

READY FOR NEXT COMPARE, OCF CLEARED

.....

ENABLE INTERRUPTS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TCR

ICIE

OCIE

TOIE

000

IEDG

$0012

reset:

000000

Unaffected

Figure 9-10. Timer Control Register (TCR)

Freescale Semiconductor, Inc.

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