68HC705JB4 datasheet(48/134 Pages) FREESCALE

48 / 134 page

GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

INPUT/OUTPUT PORTS

MC68HC05JB4

7-2

REV 2

7.2

PORT-A

Port-A is an 8-bit bi-directional port. The port-A data register is at $0000 and the

data direction register (DDRA) is at $0004. Reset does not affect the data regis-

ters, but clears the data direction registers, thereby returning the port pins to

inputs. Writing a ‘1’ to a DDR bit sets the corresponding port bit to output mode.

Each pin in Port-A has an internal pull-up resistor (50k

Ω typical) which can be

individually enabled by writing a ‘1’ to the corresponding bit in the Port-A pull-up

control register at location $0010. PA0 to PA4 have built-in schmitt triggered input

to improve noise immunity.

PA5 to PA7 port pins each has built in high current drive (10mA sink typical) for

direct LED drive. In addition, PA6 and PA7 each has optional 25mA drive which

can be enabled by Mask Option. To minimize EME (Electro-Magnetic Emission)

noise, PA6 and PA7 has slow output transition which can be enabled by writing a

‘1’ to bit-7 of the Port-B data direction register at location $0005.

PA0 to PA3 and PA4 can be used to generate IRQ and IRQ2 interrupts respec-

tively. PA0 to PA3 and PA4 cannot generate interrupts via IRQ and IRQ2 if these

port pins are conﬁgured as output pins.

If the pull-up device is enabled and the port pin is conﬁgured as output, the output

port becomes an open-drain output with 50k

Ω pull-up.

NOTE

Enabling or disabling the SLOW edge function on PA6 and PA7 does not change

the pin conﬁguration. Reading from an output pin will return the content of the

data register.

7.2.1 Port-A Data Register

Port-A PURX

Port-A DDRX

Pin Configuration

Input

Output Push/Pull

Input with 50k pull-up

Open-drain Output with 50k pull-up

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PTA

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

$0000

reset:

00000000

Freescale Semiconductor, Inc.

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