68HC705JB4 datasheet(80/134 Pages) FREESCALE

80 / 134 page

GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

UNIVERSAL SERIAL BUS MODULE

MC68HC05JB4

10-14

REV 2

Figure 10-14. Data Jitter

For low speed transmissions, the jitter time for any consecutive differential data

transitions must be within

±25 ns and within ±10 ns for any set of paired

differential data transitions. These jitter numbers include timing variations due to

differential buffer delay, rise/fall time mismatches, internal clock source jitter, and

to noise and other random effects.

10.4.3.3 Data Signal Rise and Fall Time

The output rise time and fall time are measured between 10% and 90% of the

signal. Edge transition time for the rising and falling edges of low speed signals is

75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into a

capacitive load of 350 pF. The rising and falling edges should be smooth

transitional (monotonic) when driving the cable to avoid excessive EMI.

Figure 10-15. Data Signal Rise and Fall Time

10.4.4 USB Control Logic

The USB control logic manages data movement between the CPU and the

transceiver. The control logic handles both transmit and receive operations on the

USB. It contains the logic used to manipulate the transceiver and the endpoint

registers. The logic contains byte count buffers for transmit operations that load

the active transmit endpoints byte count and use this to determine the number of

bytes to transfer. This same buffer is used for receive transactions to count the

number of bytes received and, upon the end of the transaction, transfer that

number to the receive endpoints byte count register.

CONSECUTIVE

TRANSITIONS

tPeriod

DIFFERENTIAL

DATA LINES

CROSSOVER

POINTS

PAIRED

TRANSITIONS

DIFFERENTIAL

DATA LINES

RISE TIME

FALL TIME

10%

90%

10%

LOW SPEED: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF

Freescale Semiconductor, Inc.

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