68HC705JB4 datasheet(65/134 Pages) FREESCALE

65 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

16-BIT TIMER

MOTOROLA

REV 2

9-9

IEDG - INPUT CAPTURE EDGE SELECT

The state of this read/write bit determines whether a positive or negative transi-

tion on the ICAP1 pin triggers a transfer of the contents of the timer register to

the input capture register. Reset has no effect on the IEDG bit.

1 =

Positive edge (low to high transition) triggers input capture.

0 =

Negative edge (high to low transition) triggers input capture.

9.6

TIMER STATUS REGISTER (TSR)

The timer status register (TSR) shown in Figure 9-11 contains ﬂags for the follow-

ing events:

•

An active signal on the PB0/ICAP1 pin, transferring the contents of the

timer registers to the input capture registers.

•

A match between the 16-bit counter and the output compare registers

•

An overﬂow of the timer registers from $FFFF to $0000.

Writing to any of the bits in the TSR has no effect. Reset does not change the

state of any of the ﬂag bits in the TSR.

ICF - INPUT CAPTURE FLAG

The ICF bit is automatically set when an edge of the selected polarity occurs on

the PB0/ICAP1 pin. Clear the ICF bit by reading the timer status register with

the ICF set, and then reading the low byte (ICRL, $0015) of the input capture

registers. Reset has no effect on ICF.

OCF - OUTPUT COMPARE FLAG

The OCF bit is automatically set when the value of the timer registers matches

the contents of the output compare registers. Clear the OCF bit by reading the

timer status register with the OCF set, and then accessing the low byte (OCRL,

$0017) of the output compare registers. Reset has no effect on OCF.

TOF - TIMER OVERFLOW FLAG

The TOF bit is automatically set when the 16-bit timer counter rolls over from

$FFFF to $0000. Clear the TOF bit by reading the timer status register with the

TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.

Reset has no effect on TOF.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TSR

ICF

OCF

TOF

00000

$0013

reset:

00000

U = UNAFFECTED BY RESET

Figure 9-11. Timer Status Registers (TSR)

Freescale Semiconductor, Inc.

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