68HC705JB4 datasheet(92/134 Pages) FREESCALE

92 / 134 page

GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

UNIVERSAL SERIAL BUS MODULE

MC68HC05JB4

10-26

REV 2

10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)

UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer

These write only buffers are loaded by software with data to be sent on the

USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff-

ers are shared by Endpoints 1 and 2 and depend on proper conﬁguration of the

ENDADD bit.

10.6

USB INTERRUPTS

The USB module is capable of generating interrupts and causing the CPU to

execute the USB interrupt service routine. There are three types of USB

interrupts:

•

End of Transaction interrupts signify a completed transaction (receive or

transmit)

•

Resume interrupts signify that the USB bus is reactivated after having

been suspended

•

End of Packet interrupts signify that a low speed end of packet signal

was detected

All USB interrupts share the same interrupt vector. Firmware is responsible for

determining which interrupt is active.

10.6.1 USB End of Transaction Interrupt

There are three possible end of transaction interrupts: Endpoint 0 Receive,

Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of

transaction interrupts occur as detailed in the following sections.

10.6.1.1 Receive Control Endpoint 0

For a Control OUT transaction directed at Endpoint 0, the USB module will

generate an interrupt by setting the RXD0F ﬂag in the UIR0 register. The

conditions necessary for the interrupt to occur are shown in the ﬂowchart of

Figure 10-29.

SETUP transactions cannot be stalled by the USB function. A SETUP received by

a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

UE1D0

$0028

UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0

::::::::

UE1D7

$002F

UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0

reset:

XXXXXXXX

Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)

Freescale Semiconductor, Inc.

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