68HC705JB4 datasheet(79/134 Pages) FREESCALE

79 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

UNIVERSAL SERIAL BUS MODULE

MOTOROLA

REV 2

10-13

Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range

10.4.3.1 Receiver Data Jitter

The data receivers for all types of devices must be able to properly decode the

differential data in the presence of jitter. The more of the bit cell that any data edge

can occupy and still be decoded, the more reliable the data transfer will be. Data

receivers are required to decode differential data transitions that occur in a

window plus and minus a nominal quarter bit cell from the nominal (centered) data

edge position.

Jitter will be caused by the delay mismatches and by mismatches in the source

and destination data rates (frequencies). The receive data jitter budget for low

speed is given in the electrical section of the this speciﬁcation. The speciﬁcation

includes the consecutive (next) and paired transition values for each source of

jitter.

10.4.3.2 Data Source Jitter

The source of data can have some variation (jitter) in the timing of edges of the

data

transmitted.

The

time

between

any

set

data

transitions

N x TPERIOD ± jitter time, where ‘N’ is the number of bits between the transitions

and TPERIOD is deﬁned as the actual period of the data rate. The data jitter is

measured with the same capacitive load used for maximum rise and fall times and

is measured at the crossover points of the data lines as shown in Figure 10-14.

COMMON MODE INPUT VOLTAGE (VOLTS)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

1.0

0.8

0.6

0.4

0.2

Freescale Semiconductor, Inc.

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