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DSPIC33EP128GS708 Datasheet(PDF) 184 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 184 Page - Microchip Technology |
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184 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 184 2016-2018 Microchip Technology Inc. 15.2 Output Compare Control Registers REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — bit 15 bit 8 R/W-0 U-0 U-0 HSC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits 111 = Peripheral clock (FP) 110 = Reserved 101 = Reserved 100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported) 011 = T5CLK is the clock source of the OCx 010 = T4CLK is the clock source of the OCx 001 = T3CLK is the clock source of the OCx 000 = T2CLK is the clock source of the OCx bit 9-8 Unimplemented: Read as ‘0’ bit 7 ENFLTA: Fault A Input Enable bit 1 = Output Compare Fault A input (OCFA) is enabled 0 = Output Compare Fault A input (OCFA) is disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 OCFLTA: PWM Fault A Condition Status bit 1 = PWM Fault A condition on the OCFA pin has occurred 0 = No PWM Fault A condition on the OCFA pin has occurred bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is cleared only by software Note 1: OCxR and OCxRS are double-buffered in PWM mode only. |
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