DSPIC33EP128GS708 datasheet(181/484 Pages) MICROCHIP

181 / 484 page

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DS70005258C-page 181

dsPIC33EPXXXGS70X/80X FAMILY

ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2

U-0

R/W-0

—

—IC32

bit 15

bit 8

R/W-0

HS/R/W-0

U-0

R/W-0

R/W-1

R/W-0

R/W-1

ICTRIG(2)

TRIGSTAT(3)

—

SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)

bit 7

bit 0

Legend:

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented: Read as ‘0’

bit 8

IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)

1 = Odd ICx and even ICx form a single 32-bit input capture module(1)

0 = Cascade module operation is disabled

bit 7

ICTRIG: Input Capture x Trigger Operation Select bit(2)

1 = Input source is used to trigger the input capture timer (Trigger mode)

0 = Input source is used to synchronize the input capture timer to a timer of another module

(Synchronization mode)

bit 6

TRIGSTAT: Timer Trigger Status bit(3)

1 = ICxTMR has been triggered and is running

0 = ICxTMR has not been triggered and is being held clear

bit 5

Unimplemented: Read as ‘0’

Note 1:

The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.

The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.

This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and

cleared in software.

Do not use the ICx module as its own sync or trigger source.

This option should only be selected as a trigger source and not as a synchronization source.

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