DSPIC33EP128GS708 datasheet(177/484 Pages) MICROCHIP

177 / 484 page

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DS70005258C-page 177

dsPIC33EPXXXGS70X/80X FAMILY

13.2

Timer2/3 and Timer4/5 Control Registers

TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

TON

—TSIDL

—

bit 15

bit 8

U-0

R/W-0

U-0

R/W-0

U-0

—

TGATE

TCKPS1

TCKPS0

T32

—TCS(1)

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

TON: Timerx On bit

When T32 = 1:

1 = Starts 32-bit Timerx/y

0 = Stops 32-bit Timerx/y

When T32 = 0:

1 = Starts 16-bit Timerx

0 = Stops 16-bit Timerx

bit 14

Unimplemented: Read as ‘0’

bit 13

TSIDL: Timerx Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-7

Unimplemented: Read as ‘0’

bit 6

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timerx Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3

T32: 32-Bit Timer Mode Select bit

1 = Timerx and Timery form a single 32-bit timer

0 = Timerx and Timery act as two 16-bit timers

bit 2

Unimplemented: Read as ‘0’

bit 1

TCS: Timerx Clock Source Select bit(1)

1 = External clock is from pin, TxCK (on the rising edge)

0 = Internal clock (FP)

bit 0

Unimplemented: Read as ‘0’

Note 1: The TxCK pin is not available on all devices. Refer to the “Pin Diagrams” section for the available pins.

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