DSPIC33EP128GS708 datasheet(208/484 Pages) MICROCHIP

208 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 208

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bit 3-2

CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)

IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:

If current limit is active, then CLDAT1 provides the state for the PWMxH pin.

If current limit is active, then CLDAT0 provides the state for the PWMxL pin.

IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:

CLDAT<1:0> bits are ignored.

bit 1

SWAP: SWAP PWMxH and PWMxL Pins bit

1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the

PWMxH pins

0 = PWMxH and PWMxL pins are mapped to their respective pins

bit 0

OSYNC: Output Override Synchronization bit

1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base

0 = Output overrides via the OVRDAT<1:0> bits occur on the next CPU clock boundary

Note 1:

These bits should not be changed after the PWMx module is enabled (PTEN = 1).

State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.

R/W-0

TRGCMP<12:5>

bit 15

bit 8

R/W-0

U-0

TRGCMP<4:0>

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-3

TRGCMP<12:0>: Trigger Compare Value bits

When the primary PWMx functions in the local time base, this register contains the compare values

that can trigger the ADC module.

bit 2-0

Unimplemented: Read as ‘0’

DSPIC33EP128GS708 Datasheet(PDF) 208 Page - Microchip Technology

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