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DSPIC33EP128GS708 Datasheet(PDF) 204 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 204 Page - Microchip Technology |
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204 / 484 page ![]() dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 204 2016-2018 Microchip Technology Inc. REGISTER 16-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER (x = 1 to 8)(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits (used in Independent PWM mode only) Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01 or 10); SPHASEx<15:0> = Not used • True Independent Output mode (IOCONx<11:10> = 11), SPHASEx<15:0> = Phase-shift value for PWMxL only 2: If PWMCONx<9> = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01 or 10); SPHASEx<15:0> = Not used • True Independent Output mode (IOCONx<11:10> = 11); SPHASEx<15:0> = Independent time base period value for PWMxL only • When the PHASEx/SPHASEx registers provide the local period, the valid range of values is 0x0010-0xFFF8 |
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