DSPIC33EP128GS708 datasheet(225/484 Pages) MICROCHIP

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DS70005258C-page 225

dsPIC33EPXXXGS70X/80X FAMILY

PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)

R/W-0

PTGSDLIM<15:8>

bit 15

bit 8

R/W-0

PTGSDLIM<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

PTGSDLIM<15:0>: PTG Step Delay Limit Register bits

Holds a PTG Step delay value, representing the number of additional PTG clocks, between the start

of a Step command and the completion of a Step command.

Note 1:

A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register

(Step Delay = (PTGSDLIM) + 1).

This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and

PTGSTRT = 1).

PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)

R/W-0

PTGC0LIM<15:8>

bit 15

bit 8

R/W-0

PTGC0LIM<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits

May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the

General Purpose Counter 0.

Note 1:

This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and

PTGSTRT = 1).

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