DSPIC33EP128GS708 datasheet(235/484 Pages) MICROCHIP

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DS70005258C-page 235

dsPIC33EPXXXGS70X/80X FAMILY

To set up the SPIx module for the Enhanced Buffer

Master mode of operation:

If using interrupts:

Clear the interrupt flag bits in the respective

IFSx register.

Set the interrupt enable bits in the

respective IECx register.

Write the SPIxIP bits in the respective IPCx

Write the desired settings to the SPIxCON1L,

SPIxCON1H and SPIxCON2L registers with

MSTEN (SPIxCON1L<5>) = 1.

Clear the SPIROV bit (SPIxSTATL<6>).

Select Enhanced Buffer mode by setting the

ENHBUF bit (SPIxCON1L<0>).

Enable SPIx operation by setting the SPIEN bit

(SPIxCON1L<15>).

Write the data to be transmitted to the

SPIxBUFL and SPIxBUFH registers. Transmis-

sion (and reception) will start as soon as data is

written to the SPIxBUFL and SPIxBUFH

registers.

To set up the SPIx module for the Enhanced Buffer

Slave mode of operation:

Clear the SPIxBUFL and SPIxBUFH registers.

If using interrupts:

a) Clear the interrupt flag bits in the respective

IFSx register.

b) Set the interrupt enable bits in the

respective IECx register.

Write the SPIxIP bits in the respective IPCx

Write the desired settings to the SPIxCON1L,

SPIxCON1H and SPIxCON2L registers with the

MSTEN bit (SPIxCON1L<5>) = 0.

Clear the SMP bit.

If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

Clear the SPIROV bit (SPIxSTATL<6>).

Select Enhanced Buffer mode by setting the

ENHBUF bit (SPIxCON1L<0>).

Enable SPIx operation by setting the SPIEN bit

(SPIxCON1L<15>).

FIGURE 18-2:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

Read

Write

Internal

Data Bus

SDIx

SDOx

SSx/FSYNC

SCKx

MSb

Shift

Control

Edge

Select

Enable Master Clock

Transmit

SPIxRXB

Peripheral Clock

REFO

MCLKEN

SPIxRXSR

URDTEN

TXELM<5:0> = 6’b0

MSb

Baud Rate

Generator

SSx & FSYNC

Control

Clock

Control

SPIxTXSR

Clock

Control

Receive

SPIxURDT

SPIxTXB

Edge

Select

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