| Electronic Components Datasheet Search |
|
DSPIC33EP128GS708 Datasheet(PDF) 236 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
DSPIC33EP128GS708 Datasheet(HTML) 236 Page - Microchip Technology |
|
236 / 484 page ![]() dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 236 2016-2018 Microchip Technology Inc. To set up the SPIx module for Audio mode: 1. Clear the SPIxBUFL and SPIxBUFH registers. 2. If using interrupts: a) Clear the interrupt flag bits in the respective IFSx register. b) Set the interrupt enable bits in the respective IECx register. a) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. 3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with AUDEN (SPIxCON1H<15>) = 1. 4. Clear the SPIROV bit (SPIxSTATL<6>). 5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L<15>). 6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data is written to the SPIxBUFL and SPIxBUFH registers. REGISTER 18-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL DISSDO MODE32(1,4) MODE16(1,4) SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN DISSDI DISSCK MCLKEN(3) SPIFE ENHBUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx On bit 1 = Enables module 0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Halts in CPU Idle mode 0 = Continues to operate in CPU Idle mode bit 12 DISSDO: Disable SDOx Output Port bit 1 = SDOx pin is not used by the module; pin is controlled by port function 0 = SDOx pin is controlled by the module bit 11-10 MODE32 and MODE16: Serial Word Length Select bits(1,4) Note 1: When AUDEN (SPIxCON1H<15>) = 1, this module functions as if CKE = 0, regardless of its actual value. 2: When FRMEN = 1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit = 0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW. MODE32 MODE16 AUDEN Communication 1x 0 32-Bit 01 16-Bit 00 8-Bit 11 1 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 10 32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 01 16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame 00 16-Bit FIFO, 16-Bit Channel/32-Bit Frame |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |