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DSPIC33EP128GS708 Datasheet(PDF) 471 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 471 Page - Microchip Technology |
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471 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 471 dsPIC33EPXXXGS70X/80X FAMILY INDEX A Absolute Maximum Ratings .............................................. 379 AC Characteristics ............................................................ 391 ADC Specifications ................................................... 432 Analog Current Specifications................................... 431 Analog-to-Digital Conversion Requirements............. 434 Auxiliary PLL Clock ................................................... 393 CANx I/O Requirements ........................................... 430 Capacitive Loading Requirements on Output Pins ....................................................... 391 DMA Module Requirements...................................... 437 External Clock Requirements ................................... 392 High-Speed PWMx Requirements ............................ 401 I/O Requirements...................................................... 395 I2Cx Bus Data Requirements (Master Mode) ........... 427 I2Cx Bus Data Requirements (Slave Mode) ............. 429 Input Capture x Requirements .................................. 399 Internal FRC Accuracy.............................................. 394 Internal LPRC Accuracy............................................ 394 Load Conditions ........................................................ 391 OCx/PWMx Module Requirements ........................... 400 Output Compare x Requirements ............................. 400 PLL Clock.................................................................. 393 Reset, WDT, OST, PWRT Requirements ................. 396 SPI1, SPI2 and SPI3 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Requirements ........ 405 SPI1, SPI2 and SPI3 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Requirements ........ 404 SPI1, SPI2 and SPI3 Master Mode (Half-Duplex, Transmit Only) Requirements ............................... 403 SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Requirements........ 413 SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Requirements........ 411 SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Requirements........ 407 SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Requirements........ 409 SPI3 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Requirements .................... 417 SPI3 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Requirements .................... 416 SPI3 Master Mode (Half-Duplex, Transmit Only) Requirements ................................................... 415 SPI3 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Requirements .................... 425 SPI3 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Requirements .................... 423 SPI3 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Requirements .................... 419 SPI3 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Requirements .................... 421 Temperature and Voltage Specifications .................. 391 Timer1 External Clock Requirements ....................... 397 Timer2/Timer4 External Clock Requirements ........... 398 Timer3/Timer5 External Clock Requirements ........... 398 UARTx I/O Requirements ......................................... 431 AC/DC Characteristics DACx Specifications ................................................. 435 High-Speed Analog Comparator Specifications........ 434 PGAx Specifications ................................................. 436 Analog-to-Digital Converter. See ADC. Arithmetic Logic Unit (ALU)................................................. 32 Assembler MPASM Assembler .................................................. 376 MPLAB Assembler, Linker, Librarian........................ 376 B Bit-Reversed Addressing.................................................... 58 Example...................................................................... 59 Implementation ........................................................... 58 Sequence Table (16-Entry) ........................................ 59 Block Diagrams 16-Bit Timer1 Module ............................................... 171 ADC Module ............................................................. 278 Addressing for Table Registers .................................. 63 CALL Stack Frame ..................................................... 54 CANx Module ........................................................... 312 CLCx Input Source Selection ................................... 265 CLCx Logic Function Combinatorial Options............ 264 CLCx Module............................................................ 263 Connections for On-Chip Voltage Regulator ............ 359 Constant-Current Source.......................................... 349 CPU Core ................................................................... 24 Data Access from Program Space Address Generation............................................ 60 Dedicated ADC Cores 0-3 ........................................ 279 DMA Controller ........................................................... 93 dsPIC33EPXXGS70X/80X Family.............................. 13 High-Speed Analog Comparator x............................ 338 High-Speed PWM Architecture................................. 191 Hysteresis Control .................................................... 340 I2Cx Module ............................................................. 250 Input Capture x ......................................................... 179 Interleaved PFC.......................................................... 20 MCLR Pin Connections .............................................. 18 Multiplexing Remappable Outputs for RPn .............. 140 Off-Line UPS .............................................................. 22 Oscillator System...................................................... 106 Output Compare x Module ....................................... 183 Peripheral to DMA Controller...................................... 91 PGAx Functions........................................................ 346 PGAx Module ........................................................... 345 Phase-Shifted Full-Bridge Converter.......................... 21 PLL Module .............................................................. 107 Programmer’s Model .................................................. 26 PSV Read Address Generation.................................. 51 PTG Module ............................................................. 218 Recommended Minimum Connection ........................ 18 Remappable Input for U1RX .................................... 138 Reset System ............................................................. 71 Security Segments for dsPIC33EP128GS70X/80X (Dual Partition Modes)...................................... 363 Security Segments for dsPIC33EP64GS70X/80X (Dual Partition Modes)...................................... 362 Security Segments for dsPIC33EPXXXGS70X/80X............................. 362 Shared ADC Core..................................................... 279 Shared Port Structure............................................... 127 Simplified Conceptual of High-Speed PWM ............. 192 SPIx Master, Frame Master Connection .................. 247 SPIx Master, Frame Slave Connection .................... 248 SPIx Master/Slave Connection (Enhanced Buffer Modes)................................. 247 SPIx Master/Slave Connection (Standard Mode)..... 246 SPIx Module (Enhanced Mode)................................ 235 |
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