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DSPIC33EP128GS708 Datasheet(PDF) 474 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 474 Page - Microchip Technology |
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474 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 474 2016-2018 Microchip Technology Inc. O Oscillator Control Registers ...................................................... 109 Resources................................................................. 108 Oscillator Configuration..................................................... 105 Output Compare................................................................ 183 Control Registers ...................................................... 184 Resources................................................................. 183 P Packaging ......................................................................... 443 Details ....................................................................... 445 Marking ..................................................................... 443 Peripheral Module Disable (PMD)..................................... 119 Peripheral Pin Select (PPS) .............................................. 137 Available Peripherals ................................................ 137 Available Pins ........................................................... 137 Control ...................................................................... 137 Control Registers ...................................................... 144 Input Mapping ........................................................... 138 Output Mapping ........................................................ 140 Output Selection for Remappable Pins..................... 141 Selectable Input Sources .......................................... 139 Peripheral Trigger Generator (PTG) Module..................... 217 Peripheral Trigger Generator. See PTG. Pinout I/O Descriptions (table) ............................................ 14 Power-Saving Features..................................................... 117 Clock Frequency and Switching................................ 117 Resources................................................................. 119 Program Address Space ..................................................... 33 Construction................................................................ 60 Data Access from Program Memory Using Table Instructions................................................ 61 Memory Map (dsPIC33EP128GS70X/80X Devices, Dual Partition) ..................................................... 37 Memory Map (dsPIC33EP128GS70X/80X Devices) .............................................................. 35 Memory Map (dsPIC33EP64GS70X/80X Devices, Dual Partition) ..................................................... 36 Memory Map (dsPIC33EP64GS70X/80X Devices) .................. 34 Table Read High Instructions (TBLRDH) ..................... 61 Table Read Low Instructions (TBLRDL) ...................... 61 Program Memory Interfacing with Data Memory Spaces ........................ 60 Organization................................................................ 38 Reset Vector ............................................................... 38 Programmable Gain Amplifier (PGA) ................................ 345 Description ................................................................ 346 Resources................................................................. 347 Programmable Gain Amplifier. See PGA. Programmer’s Model........................................................... 25 Register Descriptions.................................................. 25 PTG Control Registers ...................................................... 219 Introduction ............................................................... 217 Output Descriptions .................................................. 232 Step Commands and Format.................................... 229 Pulse-Width Modulator. See PWM. R Referenced Sources ........................................................... 11 Registers ACLKCON (Auxiliary Clock Divisor Control) ............. 114 ADCAL0L (ADC Calibration 0 High) ......................... 304 ADCAL0L (ADC Calibration 0 Low) .......................... 303 ADCAL1H (ADC Calibration 1 High)......................... 305 ADCMPxCON (ADC Digital Comparator x Control)............................................................. 306 ADCMPxENH (ADC Digital Comparator x Channel Enable High) ...................................... 307 ADCMPxENL (ADC Digital Comparator x Channel Enable Low) ....................................... 307 ADCON1H (ADC Control 1 High) ............................. 281 ADCON1L (ADC Control 1 Low)............................... 280 ADCON2H (ADC Control 2 High) ............................. 283 ADCON2L (ADC Control 2 Low)............................... 282 ADCON3H (ADC Control 3 High) ............................. 285 ADCON3L (ADC Control 3 Low)............................... 284 ADCON4H (ADC Control 4 High) ............................. 287 ADCON4L (ADC Control 4 Low)............................... 286 ADCON5H (ADC Control 5 High) ............................. 289 ADCON5L (ADC Control 5 Low)............................... 288 ADCORExH (Dedicated ADC Core x Control High) .................................................... 291 ADCORExL (Dedicated ADC Core x Control Low) ..................................................... 290 ADEIEH (ADC Early Interrupt Enable High) ............. 293 ADEIEL (ADC Early Interrupt Enable Low)............... 293 ADEISTATH (ADC Early Interrupt Status High) ....... 294 ADEISTATL (ADC Early Interrupt Status Low)......... 294 ADFLxCON (ADC Digital Filter x Control) ................ 308 ADIEH (ADC Interrupt Enable High)......................... 297 ADIEL (ADC Interrupt Enable Low) .......................... 297 ADLVLTRGH (ADC Level-Sensitive Trigger Control High) .................................................... 292 ADLVLTRGL (ADC Level-Sensitive Trigger Control Low) ..................................................... 292 ADMOD0H (ADC Input Mode Control 0 High).......... 295 ADMOD0L (ADC Input Mode Control 0 Low) ........... 295 ADMOD1L (ADC Input Mode Control 1 Low) ........... 296 ADSTATH (ADC Data Ready Status High) .............. 298 ADSTATL (ADC Data Ready Status Low)................ 298 ADTRIGxH (ADC Channel Trigger x Selection High) ................................................. 301 ADTRIGxL (ADC Channel Trigger x Selection Low) .................................................. 299 ALTDTRx (PWMx Alternate Dead-Time).................. 205 ANSELx (Analog Select Control x) ........................... 136 AUXCONx (PWMx Auxiliary Control) ....................... 214 CHOP (PWM Chop Clock Generator) ...................... 198 CLCxCONH (CLCx Control High)............................. 267 CLCxCONL (CLCx Control Low) .............................. 266 CLCxGLSH (CLCx Gate Logic Input Select High) ............................................. 275 CLCxGLSL (CLCx Gate Logic Input Select Low) ..... 273 CLCxSEL (CLCx Input MUX Select)......................... 268 CLKDIV (Clock Divisor) ............................................ 111 CMPxCON (Comparator x Control) .......................... 341 CMPxDAC (Comparator x DAC Control) .................. 343 CNENx (Input Change Notification Interrupt Enable x) ............................................ 135 CNPDx (Input Change Notification Pull-Down Enable x) ......................................... 136 CNPUx (Input Change Notification Pull-up Enable x) .............................................. 135 CORCON (Core Control) ...................................... 30, 85 CTXTSTAT (CPU W Register Context Status)........... 31 CxBUFPNT1 (CANx Filters 0-3 Buffer Pointer 1) ..... 322 CxBUFPNT2 (CANx Filters 4-7 Buffer Pointer 2) ..... 323 |
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