Z8F082ASH020SC datasheet(107/244 Pages) ZILOG

107 / 244 page

PS024705-0405

P R E L I M I N A R Y

UART

Z8 Encore! XP® F08xA Seriess

Product Specification

Receiving Data using the Interrupt-Driven Method

The UART Receiver interrupt indicates the availability of new data (as well as error condi-

tions). Follow these steps to configure the UART receiver for interrupt-driven operation:

1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud

rate.

2. Enable the UART pin functions by configuring the associated GPIO Port pins for

alternate function operation.

3. Execute a DI instruction to disable interrupts.

4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set

the acceptable priority.

5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.

6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode

functions, if appropriate.

–

Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR

mode.

–

Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address

matching scheme.

–

Configure the UART to interrupt on received data and errors or errors only

(interrupt on errors only is unlikely to be useful for Z8 Encore!® devices without a

DMA block)

7. Write the device address to the Address Compare Register (automatic

MULTIPROCESSOR modes only).

8. Write to the UART Control 0 register to:

–

Set the receive enable bit (REN) to enable the UART for data reception

–

Enable parity, if appropriate and if multiprocessor mode is not enabled, and select

either even or odd parity.

9. Execute an EI instruction to enable interrupts.

The UART is now configured for interrupt-driven data reception. When the UART

Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the

following:

1. Checks the UART Status 0 register to determine the source of the interrupt - error,

break, or received data.

2. Reads the data from the UART Receive Data register if the interrupt was because of

data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may

be required depending on the MULTIPROCESSOR mode bits MPMD[1:0].

3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.

Z8F082ASH020SC Datasheet(PDF) 107 Page - Zilog, Inc.

Z8F082ASH020SC Datasheet(HTML) 107 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL