Z8F082ASH020SC datasheet(111/244 Pages) ZILOG

111 / 244 page

PS024705-0405

P R E L I M I N A R Y

UART

Z8 Encore! XP® F08xA Seriess

Product Specification

Receiver Interrupts

The receiver generates an interrupt when any of the following occurs:

• A data byte is received and is available in the UART Receive Data register. This interrupt

can be disabled independently of the other receiver interrupt sources. The received data in-

terrupt occurs after the receive character has been received and placed in the Receive Data

condition before the next character is completely received.

In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on

the multiprocessor configuration and the most recent address byte.

• A break is received

• An overrun is detected

• A data framing error is detected

UART Overrun Errors

When an overrun error condition occurs the UART prevents overwriting of the valid data

currently in the Receive Data register. The Break Detect and Overrun status bits are not

displayed until after the valid data has been read.

After the valid data has been read, the UART Status 0 register is updated to indicate the

overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that

the Receive Data register contains a data byte. However, because the overrun error

occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi-

cates if the overrun was caused by a break condition on the line. After reading the status

byte indicating an overrun error, the Receive Data register must be read again to clear the

error bits is the UART Status 0 register. Updates to the Receive Data register occur only

when the next data word is received.

UART Data and Error Handling Procedure

Figure 14 illustrates the recommended procedure for use in UART receiver interrupt ser-

vice routines.

Note:

Z8F082ASH020SC Datasheet(PDF) 111 Page - Zilog, Inc.